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mlx5_cmdif_state MLX5_CMDIF_STATE_UNINITIALIZED MLX5_CMDIF_STATE_UP MLX5_CMDIF_STATE_DOWN mlx5_cmd_first mlx5_cmd_msg cmd_msg_cache max_inbox_size num_ent mlx5_cmd_mailbox mlx5_cmd_debug dbg_root mlx5_cmd_stats mlx5_cmd cmd_alloc_buf alloc_dma cmdif_rev log_sz log_stride max_reg_cmds token_lock wq_name pages_sem allowed_opcode ent_arr dbg checksum_disabled mlx5_cmd_work_ent uout uout_size cb_timeout_work lay page_queue ts1 ts2 mlx5_core_mkey usecount mlx5_uars_page bfregs reg_bitmap fp_bitmap reg_avail fp_avail mlx5_bfreg_head mlx5_bfreg_data reg_head wc_head mlx5_sq_bfreg mlx5_core_health miss_counter fatal_error crdump_size wq_lock fatal_report_work report_work fw_reporter fw_fatal_reporter mlx5_qp_table mlx5_vf_context port_guid port_guid_valid node_guid_valid mlx5_core_sriov vfs_ctx mlx5_fc_pool pool_lock fully_used partially_used available_fcs used_fcs mlx5_fc_stats counters_idr_lock counters_idr addlist dellist next_query sampling_interval bulk_query_out bulk_query_len bulk_query_alloc_failed next_bulk_query_alloc fc_pool mlx5_rl_entry rl_raw dedicated mlx5_rl_table rl_lock rl_entry mlx5_core_roce allow_rule mlx5_flow_table mlx5_flow_group mlx5_flow_handle mlx5_adev mlx5_priv irq_table eq_table pg_nb pg_wq page_root_xa fw_pages reg_pages vfs_pages host_pf_pages qp_debugfs eq_debugfs cq_debugfs cmdif_debugfs alloc_mutex pgdir_mutex pgdir_list adev_idx steering mpfs eswitch lag devcom fw_reset fc_stats rl_table ft_pool uar vhca_state_notifier sf_dev_table parent_mdev sf_hw_table sf_table mlx5_irq_table mlx5_eq_table mlx5_events mlx5_flow_steering mlx5_mpfs mlx5_eswitch mlx5_lag mlx5_devcom mlx5_fw_reset mlx5_ft_pool mlx5_vhca_state_notifier mlx5_sf_dev_table mlx5_sf_hw_table mlx5_sf_table mlx5_device_state MLX5_DEVICE_STATE_UP MLX5_DEVICE_STATE_INTERNAL_ERROR mlx5_pci_status MLX5_PCI_STATUS_DISABLED MLX5_PCI_STATUS_ENABLED mlx5_td tirs_list tdn mlx5e_hw_objs pdn mkey bfreg mlx5e_resources hw_objs dl_port uplink_netdev mlx5_rsvd_gids mlx5_pps pin_caps out_work mlx5_timer nominal_c_mult overflow_period overflow_work mlx5_clock pps_nb ptp_info pps_info mlx5_profile log_max_qp mr_cache mlx5_hca_cap hca pcam mcam qcam embedded_cpu reserved_gids roce_en mlx5_dm memic_alloc_pages mlx5_vxlan mlx5_geneve mlx5_fpga_device mlx5_accel_ipsec_ops mlx5_ib_clock_info mlx5_fw_tracer mlx5_rsc_dump mlx5_hv_vhca mlx5_cmd_cbk_t mlx5_async_ctx num_inflight inflight_done dc_key rlid udp_sport mlx5_av dqp_dct stat_rate_sl fl_mlid rmac grh_gid_fl mlx5_ib_ah ibah xmit_port mlx5_ib_create_ah_resp rdma_lookup_mode UVERBS_LOOKUP_READ UVERBS_LOOKUP_WRITE UVERBS_LOOKUP_DESTROY uverbs_obj_type_class alloc_begin alloc_commit alloc_abort lookup_get lookup_put destroy_hw remove_handle swap_uobjects uverbs_obj_type type_class num_elems enum_def uverbs_attr_spec zero_trailing alloc_and_copy mandatory is_udata objs_arr uverbs_attr_def uverbs_method_def uverbs_object_def type_attrs num_methods methods object_id command_num is_ex has_udata has_resp resp_size object_start func_is_supported func_write chain_obj_tree needs_fn_offset uverbs_ptr_attr uattr_idx enum_id uverbs_obj_attr attr_elm uverbs_api_attr uverbs_objs_arr_attr uobjects ptr_attr obj_attr objs_arr_attr uverbs_attr mlx5_srq_table mlx5_ib_flow_prio mlx5_ib_dev mdev_events cap_mask_mutex ib_active lag_active wc_support fill_delay umrc devr mkey_var slow_path_mutex odp_max_size odp_eq_mutex odp_pf_eq odp_mkeys null_mkey flow_db reset_flow_resource_lock wc_bfreg fp_bfreg delay_drop umr_fence ib_dev_list devx_whitelist_uid srq_table qp_table async_ctx devx_event_table var_table pkey_table_len mlx5_ib_flow_db prios egress_prios sniffer egress rdma_rx rdma_tx lag_demux_ft mlx5_ib_gsi_qp rx_qp outstanding_wrs outstanding_pi outstanding_ci num_qps tx_qps mlx5_ib_gsi_wr mlx5_cache_ent xlt fill_to_high_water total_mrs available_mrs umr_common mlx5_mr_cache last_add mlx5_ib_port_resources pkey_change_work mlx5_ib_resources c0 xrcdn0 xrcdn1 p0 s0 mlx5_ib_counters num_q_counters num_cong_counters num_ext_ppcnt_counters mlx5_ib_multiport mpi_lock mlx5_ib_multiport_info unref_comp mdev_refcnt is_master unaffiliate mlx5_roce tx_port_affinity last_port_state native_port_num mlx5_ib_port dbg_cc_params mlx5_ib_dbg_cc_params mlx5_eswitch_rep mlx5_ib_dbg_param mlx5_ib_delay_drop delay_drop_work events_cnt rqs_cnt dir_debugfs mlx5_ib_stage mlx5_ib_profile mlx5_ib_lb_state user_td qps mlx5_ib_pf_eq irq_nb mlx5_eq mlx5_devx_event_table devx_nb event_xa_lock event_xa mlx5_var_table bitmap_lock hw_start_addr stride_size num_var_hw_entries mlx5_port_caps has_smi ext_port_cap MLX5_CMD_OP_QUERY_HCA_CAP MLX5_CMD_OP_QUERY_ADAPTER MLX5_CMD_OP_INIT_HCA MLX5_CMD_OP_TEARDOWN_HCA MLX5_CMD_OP_ENABLE_HCA MLX5_CMD_OP_DISABLE_HCA MLX5_CMD_OP_QUERY_PAGES MLX5_CMD_OP_MANAGE_PAGES MLX5_CMD_OP_SET_HCA_CAP MLX5_CMD_OP_QUERY_ISSI MLX5_CMD_OP_SET_ISSI MLX5_CMD_OP_SET_DRIVER_VERSION MLX5_CMD_OP_QUERY_SF_PARTITION MLX5_CMD_OP_ALLOC_SF MLX5_CMD_OP_DEALLOC_SF MLX5_CMD_OP_CREATE_MKEY MLX5_CMD_OP_QUERY_MKEY MLX5_CMD_OP_DESTROY_MKEY MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS MLX5_CMD_OP_PAGE_FAULT_RESUME MLX5_CMD_OP_ALLOC_MEMIC MLX5_CMD_OP_DEALLOC_MEMIC MLX5_CMD_OP_MODIFY_MEMIC MLX5_CMD_OP_CREATE_EQ MLX5_CMD_OP_DESTROY_EQ MLX5_CMD_OP_QUERY_EQ MLX5_CMD_OP_GEN_EQE MLX5_CMD_OP_CREATE_CQ MLX5_CMD_OP_DESTROY_CQ MLX5_CMD_OP_QUERY_CQ MLX5_CMD_OP_MODIFY_CQ MLX5_CMD_OP_CREATE_QP MLX5_CMD_OP_DESTROY_QP MLX5_CMD_OP_RST2INIT_QP MLX5_CMD_OP_INIT2RTR_QP MLX5_CMD_OP_RTR2RTS_QP MLX5_CMD_OP_RTS2RTS_QP MLX5_CMD_OP_SQERR2RTS_QP MLX5_CMD_OP_2ERR_QP MLX5_CMD_OP_2RST_QP MLX5_CMD_OP_QUERY_QP MLX5_CMD_OP_SQD_RTS_QP MLX5_CMD_OP_INIT2INIT_QP MLX5_CMD_OP_CREATE_PSV MLX5_CMD_OP_DESTROY_PSV MLX5_CMD_OP_CREATE_SRQ MLX5_CMD_OP_DESTROY_SRQ MLX5_CMD_OP_QUERY_SRQ MLX5_CMD_OP_ARM_RQ MLX5_CMD_OP_CREATE_XRC_SRQ MLX5_CMD_OP_DESTROY_XRC_SRQ MLX5_CMD_OP_QUERY_XRC_SRQ MLX5_CMD_OP_ARM_XRC_SRQ MLX5_CMD_OP_CREATE_DCT MLX5_CMD_OP_DESTROY_DCT MLX5_CMD_OP_DRAIN_DCT MLX5_CMD_OP_QUERY_DCT MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION MLX5_CMD_OP_CREATE_XRQ MLX5_CMD_OP_DESTROY_XRQ MLX5_CMD_OP_QUERY_XRQ MLX5_CMD_OP_ARM_XRQ MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS MLX5_CMD_OP_RELEASE_XRQ_ERROR MLX5_CMD_OP_MODIFY_XRQ MLX5_CMD_OP_QUERY_ESW_FUNCTIONS MLX5_CMD_OP_QUERY_VPORT_STATE MLX5_CMD_OP_MODIFY_VPORT_STATE MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT MLX5_CMD_OP_QUERY_ROCE_ADDRESS MLX5_CMD_OP_SET_ROCE_ADDRESS MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT MLX5_CMD_OP_QUERY_HCA_VPORT_GID MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY MLX5_CMD_OP_QUERY_VNIC_ENV MLX5_CMD_OP_QUERY_VPORT_COUNTER MLX5_CMD_OP_ALLOC_Q_COUNTER MLX5_CMD_OP_DEALLOC_Q_COUNTER MLX5_CMD_OP_QUERY_Q_COUNTER MLX5_CMD_OP_SET_MONITOR_COUNTER MLX5_CMD_OP_ARM_MONITOR_COUNTER MLX5_CMD_OP_SET_PP_RATE_LIMIT MLX5_CMD_OP_QUERY_RATE_LIMIT MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT MLX5_CMD_OP_CREATE_QOS_PARA_VPORT MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT MLX5_CMD_OP_ALLOC_PD MLX5_CMD_OP_DEALLOC_PD MLX5_CMD_OP_ALLOC_UAR MLX5_CMD_OP_DEALLOC_UAR MLX5_CMD_OP_CONFIG_INT_MODERATION MLX5_CMD_OP_ACCESS_REG MLX5_CMD_OP_ATTACH_TO_MCG MLX5_CMD_OP_DETACH_FROM_MCG MLX5_CMD_OP_GET_DROPPED_PACKET_LOG MLX5_CMD_OP_MAD_IFC MLX5_CMD_OP_QUERY_MAD_DEMUX MLX5_CMD_OP_SET_MAD_DEMUX MLX5_CMD_OP_NOP MLX5_CMD_OP_ALLOC_XRCD MLX5_CMD_OP_DEALLOC_XRCD MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN MLX5_CMD_OP_QUERY_CONG_STATUS MLX5_CMD_OP_MODIFY_CONG_STATUS MLX5_CMD_OP_QUERY_CONG_PARAMS MLX5_CMD_OP_MODIFY_CONG_PARAMS MLX5_CMD_OP_QUERY_CONG_STATISTICS MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT MLX5_CMD_OP_SET_L2_TABLE_ENTRY MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY MLX5_CMD_OP_SET_WOL_ROL MLX5_CMD_OP_QUERY_WOL_ROL MLX5_CMD_OP_CREATE_LAG MLX5_CMD_OP_MODIFY_LAG MLX5_CMD_OP_QUERY_LAG MLX5_CMD_OP_DESTROY_LAG MLX5_CMD_OP_CREATE_VPORT_LAG MLX5_CMD_OP_DESTROY_VPORT_LAG MLX5_CMD_OP_CREATE_TIR MLX5_CMD_OP_MODIFY_TIR MLX5_CMD_OP_DESTROY_TIR MLX5_CMD_OP_QUERY_TIR MLX5_CMD_OP_CREATE_SQ MLX5_CMD_OP_MODIFY_SQ MLX5_CMD_OP_DESTROY_SQ MLX5_CMD_OP_QUERY_SQ MLX5_CMD_OP_CREATE_RQ MLX5_CMD_OP_MODIFY_RQ MLX5_CMD_OP_SET_DELAY_DROP_PARAMS MLX5_CMD_OP_DESTROY_RQ MLX5_CMD_OP_QUERY_RQ MLX5_CMD_OP_CREATE_RMP MLX5_CMD_OP_MODIFY_RMP MLX5_CMD_OP_DESTROY_RMP MLX5_CMD_OP_QUERY_RMP MLX5_CMD_OP_CREATE_TIS MLX5_CMD_OP_MODIFY_TIS MLX5_CMD_OP_DESTROY_TIS MLX5_CMD_OP_QUERY_TIS MLX5_CMD_OP_CREATE_RQT MLX5_CMD_OP_MODIFY_RQT MLX5_CMD_OP_DESTROY_RQT MLX5_CMD_OP_QUERY_RQT MLX5_CMD_OP_SET_FLOW_TABLE_ROOT MLX5_CMD_OP_CREATE_FLOW_TABLE MLX5_CMD_OP_DESTROY_FLOW_TABLE MLX5_CMD_OP_QUERY_FLOW_TABLE MLX5_CMD_OP_CREATE_FLOW_GROUP MLX5_CMD_OP_DESTROY_FLOW_GROUP MLX5_CMD_OP_QUERY_FLOW_GROUP MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY MLX5_CMD_OP_ALLOC_FLOW_COUNTER MLX5_CMD_OP_DEALLOC_FLOW_COUNTER MLX5_CMD_OP_QUERY_FLOW_COUNTER MLX5_CMD_OP_MODIFY_FLOW_TABLE MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT MLX5_CMD_OP_FPGA_CREATE_QP MLX5_CMD_OP_FPGA_MODIFY_QP MLX5_CMD_OP_FPGA_QUERY_QP MLX5_CMD_OP_FPGA_DESTROY_QP MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS MLX5_CMD_OP_CREATE_GENERAL_OBJECT MLX5_CMD_OP_MODIFY_GENERAL_OBJECT MLX5_CMD_OP_QUERY_GENERAL_OBJECT MLX5_CMD_OP_DESTROY_GENERAL_OBJECT MLX5_CMD_OP_CREATE_UCTX MLX5_CMD_OP_DESTROY_UCTX MLX5_CMD_OP_CREATE_UMEM MLX5_CMD_OP_DESTROY_UMEM MLX5_CMD_OP_SYNC_STEERING MLX5_CMD_OP_QUERY_VHCA_STATE MLX5_CMD_OP_MODIFY_VHCA_STATE MLX5_CMD_OP_MAX mlx5_ifc_query_special_contexts_out_bits reserved_at_8 dump_fill_mkey resd_lkey reserved_at_a0 mlx5_ifc_query_special_contexts_in_bits reserved_at_10 reserved_at_20 op_mod reserved_at_40 mlx5_ifc_query_cong_params_in_bits cong_protocol reserved_at_60 mlx5_ifc_mad_ifc_out_bits response_mad_packet mlx5_ifc_mad_ifc_in_bits remote_lid reserved_at_50 mad mlx5_ifc_detach_from_mcg_in_bits qpn multicast_gid mlx5_ifc_destroy_tis_in_bits tisn mlx5_ifc_destroy_tir_in_bits tirn mlx5_ifc_destroy_rqt_in_bits rqtn mlx5_ifc_dealloc_xrcd_in_bits mlx5_ifc_dealloc_transport_domain_in_bits transport_domain mlx5_ifc_dealloc_pd_in_bits mlx5_ifc_attach_to_mcg_in_bits mlx5_ifc_alloc_xrcd_out_bits mlx5_ifc_alloc_xrcd_in_bits mlx5_ifc_alloc_transport_domain_out_bits mlx5_ifc_alloc_transport_domain_in_bits IB_USER_MAD_USER_RMPP IB_MGMT_MAD_HDR IB_MGMT_MAD_DATA IB_MGMT_RMPP_HDR IB_MGMT_RMPP_DATA IB_MGMT_VENDOR_HDR IB_MGMT_VENDOR_DATA IB_MGMT_SA_HDR IB_MGMT_SA_DATA IB_MGMT_DEVICE_HDR IB_MGMT_DEVICE_DATA IB_MGMT_MAD_SIZE OPA_MGMT_MAD_DATA OPA_MGMT_RMPP_DATA OPA_MGMT_MAD_SIZE MLX5_OBJ_TYPE_SW_ICM mlx5_ifc_cmd_hca_cap_bits reserved_at_0 vhca_resource_manager hca_cap_2 reserved_at_21 event_on_vhca_state_teardown_request event_on_vhca_state_in_use event_on_vhca_state_active event_on_vhca_state_allocated event_on_vhca_state_invalid reserved_at_28 vhca_id log_max_srq_sz log_max_qp_sz event_cap reserved_at_91 isolate_vl_tc_new reserved_at_94 prio_tag_required reserved_at_99 ece_support reserved_at_a4 reg_c_preserve reserved_at_aa log_max_srq reserved_at_b0 uplink_follow ts_cqe_to_dest_cqn reserved_at_b3 max_sgl_for_optimized_performance log_max_cq_sz relaxed_ordering_write_umr relaxed_ordering_read_umr reserved_at_d2 virtio_net_device_emualtion_manager virtio_blk_device_emualtion_manager log_max_cq log_max_eq_sz relaxed_ordering_write relaxed_ordering_read log_max_mkey reserved_at_f0 reserved_at_f9 fast_teardown log_max_eq max_indirection fixed_buffer_size log_max_mrw_sz force_teardown reserved_at_111 log_max_bsf_list_size umr_extended_translation_offset log_max_klm_list_size reserved_at_120 log_max_ra_req_dc reserved_at_130 log_max_ra_res_dc reserved_at_140 release_all_pages reserved_at_147 roce_accl log_max_ra_req_qp reserved_at_150 log_max_ra_res_qp end_pad cc_query_allowed cc_modify_allowed cache_line_128byte reserved_at_165 rts2rts_qp_counters_set_id reserved_at_16a vnic_env_int_rq_oob sbcam_reg reserved_at_16e qcam_reg gid_table_size out_of_seq_cnt vport_counters retransmission_q_counters modify_rq_counter_set_id rq_delay_drop max_qp_cnt pkey_table_size vport_group_manager vhca_group_manager ib_virt eth_virt vnic_env_queue_counters ets nic_flow_table eswitch_manager device_memory mcam_reg pcam_reg port_module_event enhanced_error_q_counters ports_check reserved_at_1b3 disable_link_up beacon_led reserved_at_1c0 pps_modify log_max_msg reserved_at_1c8 max_tc temp_warn_event general_notification_event reserved_at_1d3 rol_s rol_g reserved_at_1d8 wol_s wol_g wol_a wol_b wol_m wol_u wol_p stat_rate_support reserved_at_1f0 pci_sync_for_fw_update_event reserved_at_1f2 init2_lag_tx_port_affinity reserved_at_1fa cqe_version compact_address_vector striding_rq reserved_at_202 ipoib_enhanced_offloads ipoib_basic_offloads reserved_at_205 repeated_block_disabled umr_modify_entity_size_disabled umr_modify_atomic_disabled umr_indirect_mkey_disabled dc_req_scat_data_cqe reserved_at_20d drain_sigerr cmdif_checksum sigerr_cqe reserved_at_213 wq_signature sctr_data_cqe reserved_at_216 sho tph dct eth_net_offloads reserved_at_21f cq_oi cq_resize cq_moderation reserved_at_223 cq_eq_remap block_lb_mc reserved_at_229 scqe_break_moderation cq_period_start_from_cqe reserved_at_22d apm vector_calc umr_ptr_rlky imaicl qp_packet_based reserved_at_233 qkv pkv set_deth_sqpn reserved_at_239 ud uar_4k reserved_at_241 fl_rc_qp_when_roce_disabled regexp_params uar_sz reserved_at_248 umem_uid_0 reserved_at_250 log_pg_sz bf pad_tx_eth_packet reserved_at_263 mkey_by_name reserved_at_267 log_bf_reg_size reserved_at_270 lag_dct lag_tx_port_affinity lag_native_fdb_selection reserved_at_27a lag_master num_lag_ports reserved_at_280 max_wqe_sz_sq reserved_at_2a0 max_wqe_sz_rq max_flow_counter_31_16 max_wqe_sz_sq_dc reserved_at_2e0 max_qp_mcg reserved_at_300 flow_counter_bulk_alloc log_max_mcg reserved_at_320 log_max_transport_domain reserved_at_328 log_max_pd reserved_at_330 log_max_xrcd nic_receive_steering_discard receive_discard_vport_down transmit_discard_vport_down reserved_at_343 log_max_flow_counter_bulk max_flow_counter_15_0 reserved_at_360 log_max_rq reserved_at_368 log_max_sq reserved_at_370 log_max_tir reserved_at_378 log_max_tis basic_cyclic_rcv_wqe reserved_at_381 log_max_rmp reserved_at_388 log_max_rqt reserved_at_390 log_max_rqt_size reserved_at_398 log_max_tis_per_sq ext_stride_num_range reserved_at_3a1 log_max_stride_sz_rq reserved_at_3a8 log_min_stride_sz_rq reserved_at_3b0 log_max_stride_sz_sq reserved_at_3b8 log_min_stride_sz_sq hairpin reserved_at_3c1 log_max_hairpin_queues reserved_at_3c8 log_max_hairpin_wq_data_sz reserved_at_3d0 log_max_hairpin_num_packets reserved_at_3d8 log_max_wq_sz nic_vport_change_event disable_local_lb_uc disable_local_lb_mc log_min_hairpin_wq_data_sz reserved_at_3e8 vhca_state log_max_vlan_list reserved_at_3f0 log_max_current_mc_list reserved_at_3f8 log_max_current_uc_list general_obj_types sq_ts_format rq_ts_format steering_format_version create_qp_start_hint reserved_at_460 reserved_at_462 log_max_uctx reserved_at_468 ipsec_offload log_max_umem reserved_at_480 tls_tx tls_rx log_max_l2_table reserved_at_488 log_uar_page_sz reserved_at_4a0 device_frequency_mhz device_frequency_khz reserved_at_500 num_of_uars_per_page flex_parser_protocols max_geneve_tlv_options reserved_at_568 max_geneve_tlv_option_data_len reserved_at_570 reserved_at_580 log_max_dci_stream_channels reserved_at_590 log_max_dci_errored_streams reserved_at_598 reserved_at_5a0 log_max_dek reserved_at_5b8 mini_cqe_resp_stride_index cqe_128_always cqe_compression_128 cqe_compression cqe_compression_timeout cqe_compression_max_num reserved_at_5e0 flex_parser_id_gtpu_dw_0 reserved_at_5ec rndv_offload_rc rndv_offload_dc log_tag_matching_list_sz reserved_at_5f8 log_max_xrq affiliate_nic_vport_criteria num_vhca_ports flex_parser_id_gtpu_teid reserved_at_61c sw_owner_id reserved_at_61f max_num_of_monitor_counters num_ppcnt_monitor_counters max_num_sf num_q_monitor_counters reserved_at_660 sf_set_partition reserved_at_682 log_max_sf apu reserved_at_689 log_min_sf_size max_num_sf_partitions uctx_cap reserved_at_6c0 flex_parser_id_geneve_tlv_option_0 flex_parser_id_icmp_dw1 flex_parser_id_icmp_dw0 flex_parser_id_icmpv6_dw1 flex_parser_id_icmpv6_dw0 flex_parser_id_outer_first_mpls_over_gre flex_parser_id_outer_first_mpls_over_udp_label max_num_match_definer sf_base_id flex_parser_id_gtpu_dw_2 flex_parser_id_gtpu_first_ext_dw_0 num_total_dynamic_vf_msix reserved_at_720 dynamic_msix_table_size reserved_at_740 min_dynamic_vf_msix_table_size reserved_at_750 max_dynamic_vf_msix_table_size reserved_at_760 vhca_tunnel_commands match_definer_format_supported mlx5_ifc_cong_control_r_roce_ecn_np_bits min_time_between_cnps reserved_at_c0 cnp_dscp reserved_at_d8 cnp_prio_mode cnp_802p_prio reserved_at_e0 mlx5_ifc_cong_control_r_roce_ecn_rp_bits clamp_tgt_rate reserved_at_65 clamp_tgt_rate_after_time_inc reserved_at_69 reserved_at_80 rate_to_set_on_first_cnp dce_tcp_g dce_tcp_rtt rate_reduce_monitor_period initial_alpha_value mlx5_ifc_cong_control_802_1qau_rp_bits mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp mlx5_ifc_field_select_802_1qau_rp_bits field_select_8021qaurp MLX5_SQC_STATE_RST MLX5_SQC_STATE_RDY MLX5_SQC_STATE_ERR MLX5_RQC_STATE_RST MLX5_RQC_STATE_RDY MLX5_RQC_STATE_ERR mlx5_ifc_cong_control_roce_ecn_auto_bits cong_control_802_1qau_rp cong_control_r_roce_ecn_rp cong_control_r_roce_ecn_np mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select_802_1qau_rp mlx5_ifc_modify_cong_params_in_bits field_select congestion_parameters MLX5_MAX_COMMANDS MLX5_CMD_DATA_BLOCK_SIZE MLX5_PCI_CMD_XPORT MLX5_MKEY_BSF_OCTO_SIZE MLX5_MAX_PSVS MLX5_INLINE_SEG MLX5_ADAPTER_PAGE_SHIFT MLX5_ADAPTER_PAGE_SIZE MLX5_EVENT_QUEUE_TYPE_QP MLX5_EVENT_QUEUE_TYPE_RQ MLX5_EVENT_QUEUE_TYPE_SQ MLX5_EVENT_QUEUE_TYPE_DCT MLX5_ROCE_VERSION_1 MLX5_ROCE_VERSION_2 mlx5_cap_type MLX5_CAP_GENERAL MLX5_CAP_ETHERNET_OFFLOADS MLX5_CAP_ODP MLX5_CAP_ATOMIC MLX5_CAP_ROCE MLX5_CAP_IPOIB_OFFLOADS MLX5_CAP_IPOIB_ENHANCED_OFFLOADS MLX5_CAP_FLOW_TABLE MLX5_CAP_ESWITCH_FLOW_TABLE MLX5_CAP_ESWITCH MLX5_CAP_RESERVED MLX5_CAP_VECTOR_CALC MLX5_CAP_QOS MLX5_CAP_DEBUG MLX5_CAP_RESERVED_14 MLX5_CAP_DEV_MEM MLX5_CAP_RESERVED_16 MLX5_CAP_TLS MLX5_CAP_VDPA_EMULATION MLX5_CAP_DEV_EVENT MLX5_CAP_IPSEC MLX5_CAP_GENERAL_2 MLX5_CAP_NUM mlx5_mcam_reg_groups MLX5_MCAM_REGS_FIRST_128 MLX5_MCAM_REGS_0x9080_0x90FF MLX5_MCAM_REGS_0x9100_0x917F MLX5_MCAM_REGS_NUM MLX5_BOARD_ID_LEN MLX5_CMD_TIMEOUT_MSEC MLX5_CMD_WQ_MAX_NAME MLX5_MAX_PORTS MLX5_NUM_COMMAND_CACHES MR_CACHE_LAST_STD_ENTRY MLX5_IMR_MTT_CACHE_ENTRY MLX5_IMR_KSM_CACHE_ENTRY MAX_MR_CACHE_ENTRIES uverbs_attrs_create_flow_action_esp UVERBS_ATTR_CREATE_FLOW_ACTION_ESP_HANDLE UVERBS_ATTR_FLOW_ACTION_ESP_ATTRS UVERBS_ATTR_FLOW_ACTION_ESP_ESN UVERBS_ATTR_FLOW_ACTION_ESP_KEYMAT UVERBS_ATTR_FLOW_ACTION_ESP_REPLAY UVERBS_ATTR_FLOW_ACTION_ESP_ENCAP uapi_radix_data UVERBS_API_NS_FLAG UVERBS_API_ATTR_KEY_BITS UVERBS_API_ATTR_KEY_MASK UVERBS_API_ATTR_BKEY_LEN UVERBS_API_WRITE_KEY_NUM UVERBS_API_METHOD_KEY_BITS UVERBS_API_METHOD_KEY_SHIFT UVERBS_API_METHOD_KEY_NUM_CORE UVERBS_API_METHOD_IS_WRITE UVERBS_API_METHOD_IS_WRITE_EX UVERBS_API_METHOD_KEY_NUM_DRIVER UVERBS_API_METHOD_KEY_MASK UVERBS_API_OBJ_KEY_BITS UVERBS_API_OBJ_KEY_SHIFT UVERBS_API_OBJ_KEY_NUM_CORE UVERBS_API_OBJ_KEY_NUM_DRIVER UVERBS_API_OBJ_KEY_MASK UVERBS_API_KEY_ERR MLX5_MAX_MEMIC_PAGES MLX5_MEMIC_ALLOC_SIZE_MASK mlx5_ib_dbg_cc_types MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI MLX5_IB_DBG_CC_RP_TIME_RESET MLX5_IB_DBG_CC_RP_BYTE_RESET MLX5_IB_DBG_CC_RP_THRESHOLD MLX5_IB_DBG_CC_RP_AI_RATE MLX5_IB_DBG_CC_RP_MAX_RATE MLX5_IB_DBG_CC_RP_HAI_RATE MLX5_IB_DBG_CC_RP_MIN_DEC_FAC MLX5_IB_DBG_CC_RP_MIN_RATE MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP MLX5_IB_DBG_CC_RP_DCE_TCP_G MLX5_IB_DBG_CC_RP_DCE_TCP_RTT MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE MLX5_IB_DBG_CC_RP_GD MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS MLX5_IB_DBG_CC_NP_CNP_DSCP MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE MLX5_IB_DBG_CC_NP_CNP_PRIO MLX5_IB_DBG_CC_MAX mlx5_ib_stages MLX5_IB_STAGE_INIT MLX5_IB_STAGE_FS MLX5_IB_STAGE_CAPS MLX5_IB_STAGE_NON_DEFAULT_CB MLX5_IB_STAGE_ROCE MLX5_IB_STAGE_QP MLX5_IB_STAGE_SRQ MLX5_IB_STAGE_DEVICE_RESOURCES MLX5_IB_STAGE_DEVICE_NOTIFIER MLX5_IB_STAGE_ODP MLX5_IB_STAGE_COUNTERS MLX5_IB_STAGE_CONG_DEBUGFS MLX5_IB_STAGE_UAR MLX5_IB_STAGE_BFREG MLX5_IB_STAGE_PRE_IB_REG_UMR MLX5_IB_STAGE_WHITELIST_UID MLX5_IB_STAGE_IB_REG MLX5_IB_STAGE_POST_IB_REG_UMR MLX5_IB_STAGE_DELAY_DROP MLX5_IB_STAGE_RESTRACK MLX5_IB_STAGE_MAX mlx5_ib_cong_node_type MLX5_IB_RROCE_ECN_RP MLX5_IB_RROCE_ECN_NP ib_counters_description IB_COUNTER_PACKETS IB_COUNTER_BYTES MLX5_SHARED_RESOURCE_UID mlx5_ifc_phys_layer_cntrs_bits time_since_last_clear_high time_since_last_clear_low symbol_errors_high symbol_errors_low sync_headers_errors_high sync_headers_errors_low edpl_bip_errors_lane0_high edpl_bip_errors_lane0_low edpl_bip_errors_lane1_high edpl_bip_errors_lane1_low edpl_bip_errors_lane2_high edpl_bip_errors_lane2_low edpl_bip_errors_lane3_high edpl_bip_errors_lane3_low fc_fec_corrected_blocks_lane0_high fc_fec_corrected_blocks_lane0_low fc_fec_corrected_blocks_lane1_high fc_fec_corrected_blocks_lane1_low fc_fec_corrected_blocks_lane2_high fc_fec_corrected_blocks_lane2_low fc_fec_corrected_blocks_lane3_high fc_fec_corrected_blocks_lane3_low fc_fec_uncorrectable_blocks_lane0_high fc_fec_uncorrectable_blocks_lane0_low fc_fec_uncorrectable_blocks_lane1_high fc_fec_uncorrectable_blocks_lane1_low fc_fec_uncorrectable_blocks_lane2_high fc_fec_uncorrectable_blocks_lane2_low fc_fec_uncorrectable_blocks_lane3_high fc_fec_uncorrectable_blocks_lane3_low rs_fec_corrected_blocks_high rs_fec_corrected_blocks_low rs_fec_uncorrectable_blocks_high rs_fec_uncorrectable_blocks_low rs_fec_no_errors_blocks_high rs_fec_no_errors_blocks_low rs_fec_single_error_blocks_high rs_fec_single_error_blocks_low rs_fec_corrected_symbols_total_high rs_fec_corrected_symbols_total_low rs_fec_corrected_symbols_lane0_high rs_fec_corrected_symbols_lane0_low rs_fec_corrected_symbols_lane1_high rs_fec_corrected_symbols_lane1_low rs_fec_corrected_symbols_lane2_high rs_fec_corrected_symbols_lane2_low rs_fec_corrected_symbols_lane3_high rs_fec_corrected_symbols_lane3_low link_down_events successful_recovery_events reserved_at_640 mlx5_ifc_phys_layer_statistical_cntrs_bits phy_received_bits_high phy_received_bits_low phy_symbol_errors_high phy_symbol_errors_low phy_corrected_bits_high phy_corrected_bits_low phy_corrected_bits_lane0_high phy_corrected_bits_lane0_low phy_corrected_bits_lane1_high phy_corrected_bits_lane1_low phy_corrected_bits_lane2_high phy_corrected_bits_lane2_low phy_corrected_bits_lane3_high phy_corrected_bits_lane3_low reserved_at_200 mlx5_ifc_ib_port_cntrs_grp_data_layout_bits symbol_error_counter link_error_recovery_counter link_downed_counter port_rcv_errors port_rcv_remote_physical_errors port_rcv_switch_relay_errors port_xmit_discards port_xmit_constraint_errors port_rcv_constraint_errors reserved_at_70 link_overrun_errors vl_15_dropped port_xmit_wait mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits transmit_queue_high transmit_queue_low no_buffer_discard_uc_high no_buffer_discard_uc_low mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits wred_discard_high wred_discard_low ecn_marked_tc_high ecn_marked_tc_low mlx5_ifc_eth_per_prio_grp_data_layout_bits rx_octets_high rx_octets_low rx_frames_high rx_frames_low tx_octets_high tx_octets_low reserved_at_180 tx_frames_high tx_frames_low rx_pause_high rx_pause_low rx_pause_duration_high rx_pause_duration_low tx_pause_high tx_pause_low tx_pause_duration_high tx_pause_duration_low rx_pause_transition_high rx_pause_transition_low rx_discards_high rx_discards_low device_stall_minor_watermark_cnt_high device_stall_minor_watermark_cnt_low device_stall_critical_watermark_cnt_high device_stall_critical_watermark_cnt_low mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits port_transmit_wait_high port_transmit_wait_low rx_buffer_almost_full_high rx_buffer_almost_full_low rx_buffer_full_high rx_buffer_full_low rx_icrc_encapsulated_high rx_icrc_encapsulated_low mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits dot3stats_alignment_errors_high dot3stats_alignment_errors_low dot3stats_fcs_errors_high dot3stats_fcs_errors_low dot3stats_single_collision_frames_high dot3stats_single_collision_frames_low dot3stats_multiple_collision_frames_high dot3stats_multiple_collision_frames_low dot3stats_sqe_test_errors_high dot3stats_sqe_test_errors_low dot3stats_deferred_transmissions_high dot3stats_deferred_transmissions_low dot3stats_late_collisions_high dot3stats_late_collisions_low dot3stats_excessive_collisions_high dot3stats_excessive_collisions_low dot3stats_internal_mac_transmit_errors_high dot3stats_internal_mac_transmit_errors_low dot3stats_carrier_sense_errors_high dot3stats_carrier_sense_errors_low dot3stats_frame_too_longs_high dot3stats_frame_too_longs_low dot3stats_internal_mac_receive_errors_high dot3stats_internal_mac_receive_errors_low dot3stats_symbol_errors_high dot3stats_symbol_errors_low dot3control_in_unknown_opcodes_high dot3control_in_unknown_opcodes_low dot3in_pause_frames_high dot3in_pause_frames_low dot3out_pause_frames_high dot3out_pause_frames_low reserved_at_400 mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits ether_stats_drop_events_high ether_stats_drop_events_low ether_stats_octets_high ether_stats_octets_low ether_stats_pkts_high ether_stats_pkts_low ether_stats_broadcast_pkts_high ether_stats_broadcast_pkts_low ether_stats_multicast_pkts_high ether_stats_multicast_pkts_low ether_stats_crc_align_errors_high ether_stats_crc_align_errors_low ether_stats_undersize_pkts_high ether_stats_undersize_pkts_low ether_stats_oversize_pkts_high ether_stats_oversize_pkts_low ether_stats_fragments_high ether_stats_fragments_low ether_stats_jabbers_high ether_stats_jabbers_low ether_stats_collisions_high ether_stats_collisions_low ether_stats_pkts64octets_high ether_stats_pkts64octets_low ether_stats_pkts65to127octets_high ether_stats_pkts65to127octets_low ether_stats_pkts128to255octets_high ether_stats_pkts128to255octets_low ether_stats_pkts256to511octets_high ether_stats_pkts256to511octets_low ether_stats_pkts512to1023octets_high ether_stats_pkts512to1023octets_low ether_stats_pkts1024to1518octets_high ether_stats_pkts1024to1518octets_low ether_stats_pkts1519to2047octets_high ether_stats_pkts1519to2047octets_low ether_stats_pkts2048to4095octets_high ether_stats_pkts2048to4095octets_low ether_stats_pkts4096to8191octets_high ether_stats_pkts4096to8191octets_low ether_stats_pkts8192to10239octets_high ether_stats_pkts8192to10239octets_low reserved_at_540 mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits if_in_octets_high if_in_octets_low if_in_ucast_pkts_high if_in_ucast_pkts_low if_in_discards_high if_in_discards_low if_in_errors_high if_in_errors_low if_in_unknown_protos_high if_in_unknown_protos_low if_out_octets_high if_out_octets_low if_out_ucast_pkts_high if_out_ucast_pkts_low if_out_discards_high if_out_discards_low if_out_errors_high if_out_errors_low if_in_multicast_pkts_high if_in_multicast_pkts_low if_in_broadcast_pkts_high if_in_broadcast_pkts_low if_out_multicast_pkts_high if_out_multicast_pkts_low if_out_broadcast_pkts_high if_out_broadcast_pkts_low reserved_at_340 mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits a_frames_transmitted_ok_high a_frames_transmitted_ok_low a_frames_received_ok_high a_frames_received_ok_low a_frame_check_sequence_errors_high a_frame_check_sequence_errors_low a_alignment_errors_high a_alignment_errors_low a_octets_transmitted_ok_high a_octets_transmitted_ok_low a_octets_received_ok_high a_octets_received_ok_low a_multicast_frames_xmitted_ok_high a_multicast_frames_xmitted_ok_low a_broadcast_frames_xmitted_ok_high a_broadcast_frames_xmitted_ok_low a_multicast_frames_received_ok_high a_multicast_frames_received_ok_low a_broadcast_frames_received_ok_high a_broadcast_frames_received_ok_low a_in_range_length_errors_high a_in_range_length_errors_low a_out_of_range_length_field_high a_out_of_range_length_field_low a_frame_too_long_errors_high a_frame_too_long_errors_low a_symbol_error_during_carrier_high a_symbol_error_during_carrier_low a_mac_control_frames_transmitted_high a_mac_control_frames_transmitted_low a_mac_control_frames_received_high a_mac_control_frames_received_low a_unsupported_opcodes_received_high a_unsupported_opcodes_received_low a_pause_mac_ctrl_frames_received_high a_pause_mac_ctrl_frames_received_low a_pause_mac_ctrl_frames_transmitted_high a_pause_mac_ctrl_frames_transmitted_low reserved_at_4c0 mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits eth_802_3_cntrs_grp_data_layout eth_2863_cntrs_grp_data_layout eth_2819_cntrs_grp_data_layout eth_3635_cntrs_grp_data_layout eth_extended_cntrs_grp_data_layout eth_per_prio_grp_data_layout eth_per_tc_prio_grp_data_layout eth_per_tc_congest_prio_grp_data_layout ib_port_cntrs_grp_data_layout phys_layer_cntrs phys_layer_statistical_cntrs mlx5_ifc_query_q_counter_in_bits reserved_at_c1 counter_set_id mlx5_ifc_dealloc_q_counter_in_bits mlx5_ifc_alloc_q_counter_out_bits mlx5_ifc_alloc_q_counter_in_bits mlx5_ifc_ppcnt_reg_bits swid pnat reserved_at_12 mlx5_ifc_pcam_enhanced_features_bits fec_50G_per_lane_in_pplm rx_icrc_encapsulated_counter reserved_at_6e ptys_extended_ethernet reserved_at_73 pfcc_mask reserved_at_77 per_lane_error_counters rx_buffer_fullness_counters ptys_connector_type reserved_at_7d ppcnt_discard_group ppcnt_statistical_group mlx5_ifc_pcam_regs_5000_to_507f_bits port_access_reg_cap_mask_127_to_96 port_access_reg_cap_mask_95_to_64 port_access_reg_cap_mask_63_to_36 pplm port_access_reg_cap_mask_34_to_32 port_access_reg_cap_mask_31_to_13 pbmc pptb port_access_reg_cap_mask_10_to_09 ppcnt port_access_reg_cap_mask_07_to_00 regs_5000_to_507f enhanced_features mlx5_ifc_pcam_reg_bits feature_group access_reg_group port_access_reg_cap_mask feature_cap_mask MLX5_IEEE_802_3_COUNTERS_GROUP MLX5_RFC_2863_COUNTERS_GROUP MLX5_RFC_2819_COUNTERS_GROUP MLX5_RFC_3635_COUNTERS_GROUP MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP MLX5_PER_PRIORITY_COUNTERS_GROUP MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP MLX5_PHYSICAL_LAYER_COUNTERS_GROUP MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP MLX5_INFINIBAND_PORT_COUNTERS_GROUP MLX5_REG_QPTS MLX5_REG_QETCR MLX5_REG_QTCT MLX5_REG_QPDPM MLX5_REG_QCAM MLX5_REG_DCBX_PARAM MLX5_REG_DCBX_APP MLX5_REG_FPGA_CAP MLX5_REG_FPGA_CTRL MLX5_REG_FPGA_ACCESS_REG MLX5_REG_CORE_DUMP MLX5_REG_PCAP MLX5_REG_PMTU MLX5_REG_PTYS MLX5_REG_PAOS MLX5_REG_PFCC MLX5_REG_PPCNT MLX5_REG_PPTB MLX5_REG_PBMC MLX5_REG_PMAOS MLX5_REG_PUDE MLX5_REG_PMPE MLX5_REG_PELC MLX5_REG_PVLC MLX5_REG_PCMR MLX5_REG_PDDR MLX5_REG_PMLP MLX5_REG_PPLM MLX5_REG_PCAM MLX5_REG_NODE_DESC MLX5_REG_HOST_ENDIANNESS MLX5_REG_MCIA MLX5_REG_MFRL MLX5_REG_MLCR MLX5_REG_MTRC_CAP MLX5_REG_MTRC_CONF MLX5_REG_MTRC_STDB MLX5_REG_MTRC_CTRL MLX5_REG_MPEIN MLX5_REG_MPCNT MLX5_REG_MTPPS MLX5_REG_MTPPSE MLX5_REG_MTUTC MLX5_REG_MPEGC MLX5_REG_MCQS MLX5_REG_MCQI MLX5_REG_MCC MLX5_REG_MCDA MLX5_REG_MCAM MLX5_REG_MIRC MLX5_REG_SBCAM MLX5_REG_RESOURCE_DUMP mlx5_ib_flow_counters_desc mlx5_ib_flow_counters_data counters_data mlx5_ib_create_flow ncounters_data rep_data vlan_refcount esw mlx5_read_counters_attr hw_cntrs_hndl mlx5_fc mlx5_ib_counters_type MLX5_IB_COUNTERS_FLOW mlx5_ib_mcounters ibcntrs counters_num cntrs_max_index mcntrs_mutex MLX5_ESWITCH_NONE MLX5_ESWITCH_LEGACY MLX5_ESWITCH_OFFLOADS REP_ETH REP_IB NUM_REP_TYPES mlx5_eswitch_rep_data mlx5_ib_counter ib_uverbs_ex_create_cq_flags IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN rdma_network_type RDMA_NETWORK_IB RDMA_NETWORK_ROCE_V1 RDMA_NETWORK_IPV4 RDMA_NETWORK_IPV6 ib_wc_flags IB_WC_GRH IB_WC_WITH_IMM IB_WC_WITH_INVALIDATE IB_WC_IP_CSUM_OK IB_WC_WITH_SMAC IB_WC_WITH_VLAN IB_WC_WITH_NETWORK_HDR_TYPE ib_access_flags IB_ACCESS_LOCAL_WRITE IB_ACCESS_REMOTE_WRITE IB_ACCESS_REMOTE_READ IB_ACCESS_REMOTE_ATOMIC IB_ACCESS_MW_BIND IB_ZERO_BASED IB_ACCESS_ON_DEMAND IB_ACCESS_HUGETLB IB_ACCESS_RELAXED_ORDERING IB_ACCESS_OPTIONAL IB_ACCESS_SUPPORTED ib_umem owning_mm is_odp is_dmabuf is_peer mlx5_ifc_resize_field_select_bits resize_field_select mlx5_ifc_modify_field_select_bits modify_field_select mlx5_ifc_cqc_bits reserved_at_4 dbr_umem_valid apu_cq cqe_sz reserved_at_c scqe_break_moderation_en oi cqe_comp_en mini_cqe_res_format reserved_at_18 page_offset reserved_at_5a log_cq_size uar_page cq_period cq_max_count c_eqn_or_apu_element log_page_size reserved_at_c8 reserved_at_100 last_notified_index last_solicit_index consumer_counter reserved_at_160 producer_counter dbr_addr mlx5_ifc_modify_field_select_resize_field_select_auto_bits mlx5_ifc_modify_cq_in_bits cqn modify_field_select_resize_field_select cq_umem_valid reserved_at_2e1 pas mlx5_ifc_create_cq_in_bits mlx5_event MLX5_EVENT_TYPE_NOTIFY_ANY MLX5_EVENT_TYPE_COMP MLX5_EVENT_TYPE_PATH_MIG MLX5_EVENT_TYPE_COMM_EST MLX5_EVENT_TYPE_SQ_DRAINED MLX5_EVENT_TYPE_SRQ_LAST_WQE MLX5_EVENT_TYPE_SRQ_RQ_LIMIT MLX5_EVENT_TYPE_CQ_ERROR MLX5_EVENT_TYPE_WQ_CATAS_ERROR MLX5_EVENT_TYPE_PATH_MIG_FAILED MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR MLX5_EVENT_TYPE_WQ_ACCESS_ERROR MLX5_EVENT_TYPE_SRQ_CATAS_ERROR MLX5_EVENT_TYPE_INTERNAL_ERROR MLX5_EVENT_TYPE_PORT_CHANGE MLX5_EVENT_TYPE_GPIO_EVENT MLX5_EVENT_TYPE_PORT_MODULE_EVENT MLX5_EVENT_TYPE_TEMP_WARN_EVENT MLX5_EVENT_TYPE_XRQ_ERROR MLX5_EVENT_TYPE_REMOTE_CONFIG MLX5_EVENT_TYPE_GENERAL_EVENT MLX5_EVENT_TYPE_MONITOR_COUNTER MLX5_EVENT_TYPE_PPS_EVENT MLX5_EVENT_TYPE_DB_BF_CONGESTION MLX5_EVENT_TYPE_STALL_EVENT MLX5_EVENT_TYPE_CMD MLX5_EVENT_TYPE_PAGE_REQUEST MLX5_EVENT_TYPE_PAGE_FAULT MLX5_EVENT_TYPE_NIC_VPORT_CHANGE MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED MLX5_EVENT_TYPE_VHCA_STATE_CHANGE MLX5_EVENT_TYPE_DCT_DRAINED MLX5_EVENT_TYPE_DCT_KEY_VIOLATION MLX5_EVENT_TYPE_FPGA_ERROR MLX5_EVENT_TYPE_FPGA_QP_ERROR MLX5_EVENT_TYPE_DEVICE_TRACER MLX5_EVENT_TYPE_MAX MLX5_OPCODE_NOP MLX5_OPCODE_SEND_INVAL MLX5_OPCODE_RDMA_WRITE MLX5_OPCODE_RDMA_WRITE_IMM MLX5_OPCODE_SEND MLX5_OPCODE_SEND_IMM MLX5_OPCODE_LSO MLX5_OPCODE_RDMA_READ MLX5_OPCODE_ATOMIC_CS MLX5_OPCODE_ATOMIC_FA MLX5_OPCODE_ATOMIC_MASKED_CS MLX5_OPCODE_ATOMIC_MASKED_FA MLX5_OPCODE_BIND_MW MLX5_OPCODE_CONFIG_CMD MLX5_OPCODE_ENHANCED_MPSW MLX5_RECV_OPCODE_RDMA_WRITE_IMM MLX5_RECV_OPCODE_SEND MLX5_RECV_OPCODE_SEND_IMM MLX5_RECV_OPCODE_SEND_INVAL MLX5_CQE_OPCODE_ERROR MLX5_CQE_OPCODE_RESIZE MLX5_OPCODE_SET_PSV MLX5_OPCODE_GET_PSV MLX5_OPCODE_CHECK_PSV MLX5_OPCODE_DUMP MLX5_OPCODE_RGET_PSV MLX5_OPCODE_RCHECK_PSV MLX5_OPCODE_UMR MLX5_OPCODE_ACCESS_ASO mlx5_eqe_comp mlx5_eqe_qp_srq qp_srq_n mlx5_eqe_cq_err mlx5_eqe_xrq_err type_xrqn mlx5_eqe_port_state mlx5_eqe_gpio gpio_event mlx5_eqe_congestion congestion_level mlx5_eqe_stall_vl port_vl mlx5_eqe_cmd mlx5_eqe_page_req ec_function wqe_index pftype_wq r_key rdma_op_len rdma_va pftype_token rdma mlx5_eqe_page_fault bytes_committed mlx5_eqe_vport_change vport_num mlx5_eqe_port_module reserved_at_2 module_status time_sec time_nsec mlx5_eqe_pps mlx5_eqe_dct dctn mlx5_eqe_temp_warning sensor_warning_msb sensor_warning_lsb mlx5_eqe_sync_fw_update sync_rst_state mlx5_eqe_vhca_state function_id ev_data qp_srq cq_err stall_vl req_pages vport_change port_module temp_warning xrq_err sync_fw_update mlx5_eqe mlx5_err_cqe srqn vendor_err_synd s_wqe_opcode_qpn wqe_counter op_own inval_rkey ft_metadata mlx5_cqe64 tls_outer_l3_tunneled wqe_id lro_tcppsh_abort_dupack lro_min_ttl lro_tcp_win lro_ack_seq_num rss_hash_result rss_hash_type ml_path check_sum flags_rqpn hds_ip_ext l4_l3_hdr_type rsvd40 byte_cnt timestamp_h timestamp_l sop_drop_qpn MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 CQE_L2_OK CQE_L3_OK CQE_L4_OK mlx5_sig_err_cqe expected_trans_sig actual_trans_sig expected_reftag actual_reftag rsvd22 err_offset rsvd30 rsvd38 dbg_rsc_type MLX5_DBG_RSC_QP MLX5_DBG_RSC_EQ MLX5_DBG_RSC_CQ mlx5_field_desc mlx5_rsc_debug mlx5_buf_list mlx5_frag_buf mlx5_frag_buf_ctrl sz_m1 frag_sz_m1 strides_offset log_frag_strides psv_layout mlx5_core_psv psv_idx psv mlx5_core_sig_ctx psv_memory psv_wire err_item sig_status_checked sig_err_exists sigerr_count mlx5_res_type MLX5_RES_QP MLX5_RES_RQ MLX5_RES_SQ MLX5_RES_SRQ MLX5_RES_XSRQ MLX5_RES_XRQ MLX5_RES_DCT mlx5_core_rsc_common mlx5_rate_limit max_burst_sz typical_pkt_sz mlx5_db_pgdir mlx5_ib_user_db_page mlx5_db mlx5_core_cq set_ci_db arm_db irqn cons_index arm_sn tasklet_ctx reset_notify_added reset_notify mlx5_eq_comp MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR MLX5_CQE_SYNDROME_LOCAL_PROT_ERR MLX5_CQE_SYNDROME_WR_FLUSH_ERR MLX5_CQE_SYNDROME_MW_BIND_ERR MLX5_CQE_SYNDROME_BAD_RESP_ERR MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR MLX5_CQE_SYNDROME_REMOTE_OP_ERR MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR MLX5_CQE_OWNER_MASK MLX5_CQE_REQ MLX5_CQE_RESP_WR_IMM MLX5_CQE_RESP_SEND MLX5_CQE_RESP_SEND_IMM MLX5_CQE_RESP_SEND_INV MLX5_CQE_RESIZE_CQ MLX5_CQE_SIG_ERR MLX5_CQE_REQ_ERR MLX5_CQE_RESP_ERR MLX5_CQE_INVALID MLX5_CQ_OPMOD_RESIZE MLX5_MODIFY_CQ_MASK_LOG_SIZE MLX5_MODIFY_CQ_MASK_PG_OFFSET MLX5_MODIFY_CQ_MASK_PG_SIZE CQE_STRIDE_64 CQE_STRIDE_128 CQE_STRIDE_128_PAD MLX5_CQ_DB_REQ_NOT_SOL MLX5_CQ_DB_REQ_NOT mlx5_core_qp mlx5_core_dct mqp drained mlx5_ib_cqe_comp_res_format MLX5_IB_CQE_RES_FORMAT_HASH MLX5_IB_CQE_RES_FORMAT_CSUM MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX mlx5_ib_create_cq_flags MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS mlx5_ib_create_cq buf_addr db_addr cqe_size cqe_comp_res_format uar_page_index mlx5_ib_resize_cq mlx5_core_srq max_gs max_avail_gather wqe_shift mlx5_bfreg_info sys_pages num_low_latency_bfregs lib_uar_4k lib_uar_dyn num_sys_pages num_static_sys_pages total_num_bfregs num_dyn_bfregs mlx5_ib_ucontext ibucontext db_page_list db_page_mutex bfregi lib_caps devx_uid wr_list mlx5_ib_wq wrid wr_data w_list wqe_head unsig_count max_post cur_post last_poll cur_edge mlx5_ib_ubuffer mlx5_ib_qp_base container_mibqp mlx5_ib_qp ibqp sq_signal_bits next_fence is_rss bfregn qps_list cq_recv_list cq_send_list underlay_qpn flags_en counter_pending gsi_lag_port mlx5_ib_qp_trans xrcdn alt_port atomic_rd_en resp_depth mlx5_ib_rss_qp mlx5_ib_rq mlx5_ib_sq mlx5_ib_raw_packet_qp mlx5_bf mlx5_ib_dct mdct trans_qp raw_packet_qp rss_qp mlx5_ib_cq_buf frag_buf nent mlx5_ib_cq_pr_flags MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS mlx5_ib_cq ibcq mcq resize_mutex resize_buf resize_umem list_send_qp list_recv_qp wc_list notify_flags notify_work private_flags mlx5_ib_wc mlx5_ib_srq ibsrq msrq wqe_ctr wq_sig MLX5_CQE_RES_FORMAT_HASH MLX5_CQE_RES_FORMAT_CSUM MLX5_CQE_RES_FORMAT_CSUM_STRIDX uverbs_default_objects UVERBS_OBJECT_DEVICE UVERBS_OBJECT_PD UVERBS_OBJECT_COMP_CHANNEL UVERBS_OBJECT_CQ UVERBS_OBJECT_QP UVERBS_OBJECT_SRQ UVERBS_OBJECT_AH UVERBS_OBJECT_MR UVERBS_OBJECT_MW UVERBS_OBJECT_FLOW UVERBS_OBJECT_XRCD UVERBS_OBJECT_RWQ_IND_TBL UVERBS_OBJECT_WQ UVERBS_OBJECT_FLOW_ACTION UVERBS_OBJECT_DM UVERBS_OBJECT_COUNTERS UVERBS_OBJECT_ASYNC_EVENT uverbs_methods_dm UVERBS_METHOD_DM_ALLOC UVERBS_METHOD_DM_FREE uverbs_attr_type UVERBS_ATTR_TYPE_NA UVERBS_ATTR_TYPE_PTR_IN UVERBS_ATTR_TYPE_PTR_OUT UVERBS_ATTR_TYPE_IDR UVERBS_ATTR_TYPE_FD UVERBS_ATTR_TYPE_ENUM_IN UVERBS_ATTR_TYPE_IDRS_ARRAY uverbs_obj_access UVERBS_ACCESS_READ UVERBS_ACCESS_WRITE UVERBS_ACCESS_NEW UVERBS_ACCESS_DESTROY uapi_definition_kind UAPI_DEF_END UAPI_DEF_OBJECT_START UAPI_DEF_WRITE UAPI_DEF_CHAIN_OBJ_TREE UAPI_DEF_CHAIN UAPI_DEF_IS_SUPPORTED_FUNC UAPI_DEF_IS_SUPPORTED_DEV_FN mlx5_ifc_flow_table_fields_supported_bits outer_dmac outer_smac outer_ether_type outer_ip_version outer_first_prio outer_first_cfi outer_first_vid outer_ipv4_ttl outer_second_prio outer_second_cfi outer_second_vid reserved_at_b outer_sip outer_dip outer_frag outer_ip_protocol outer_ip_ecn outer_ip_dscp outer_udp_sport outer_udp_dport outer_tcp_sport outer_tcp_dport outer_tcp_flags outer_gre_protocol outer_gre_key outer_vxlan_vni outer_geneve_vni outer_geneve_oam outer_geneve_protocol_type outer_geneve_opt_len reserved_at_1e source_eswitch_port inner_dmac inner_smac inner_ether_type inner_ip_version inner_first_prio inner_first_cfi inner_first_vid reserved_at_27 inner_second_prio inner_second_cfi inner_second_vid reserved_at_2b inner_sip inner_dip inner_frag inner_ip_protocol inner_ip_ecn inner_ip_dscp inner_udp_sport inner_udp_dport inner_tcp_sport inner_tcp_dport inner_tcp_flags reserved_at_37 geneve_tlv_option_0_data geneve_tlv_option_0_exist reserved_at_42 outer_first_mpls_over_udp outer_first_mpls_over_gre inner_first_mpls outer_first_mpls reserved_at_55 outer_esp_spi reserved_at_58 bth_dst_qp reserved_at_5b metadata_reg_c_7 metadata_reg_c_6 metadata_reg_c_5 metadata_reg_c_4 metadata_reg_c_3 metadata_reg_c_2 metadata_reg_c_1 metadata_reg_c_0 mlx5_ifc_flow_table_prop_layout_bits ft_support reserved_at_1 flow_counter flow_modify_en modify_root identified_miss_table_mode flow_table_modify reformat decap reserved_at_9 pop_vlan push_vlan pop_vlan_2 push_vlan_2 reformat_and_vlan_action sw_owner reformat_l3_tunnel_to_l2 reformat_l2_to_l3_tunnel reformat_and_modify_action ignore_flow_level reserved_at_16 table_miss_action_domain termination_table reformat_and_fwd_to_table reserved_at_1a ipsec_encrypt ipsec_decrypt sw_owner_v2 reserved_at_1f termination_table_raw_traffic log_max_ft_size log_max_modify_header_context max_modify_header_actions max_ft_level execute_aso reserved_at_47 reformat_insert reformat_remove reserver_at_64 log_max_ft_num log_max_flow_counter log_max_destination log_max_flow ft_field_support ft_field_bitmask_support mlx5_ifc_flow_table_nic_cap_bits nic_rx_multi_path_tirs nic_rx_multi_path_tirs_fts allow_sniffer_and_nic_rx_shared_tir reserved_at_3 sw_owner_reformat_supported encap_general_header log_max_packet_reformat_context reserved_at_30 max_encap_header_size flow_table_properties_nic_receive flow_table_properties_nic_receive_rdma flow_table_properties_nic_receive_sniffer flow_table_properties_nic_transmit flow_table_properties_nic_transmit_rdma flow_table_properties_nic_transmit_sniffer reserved_at_e00 sw_steering_nic_rx_action_drop_icm_address sw_steering_nic_tx_action_drop_icm_address sw_steering_nic_tx_action_allow_icm_address reserved_at_20c0 mlx5_ifc_device_mem_cap_bits memic log_min_memic_alloc_size log_max_memic_addr_alignment memic_bar_start_addr memic_bar_size max_memic_size steering_sw_icm_start_address log_header_modify_sw_icm_size reserved_at_110 log_sw_icm_alloc_granularity log_steering_sw_icm_size header_modify_sw_icm_start_address memic_operations reserved_at_220 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC mlx5_ifc_modify_memic_in_bits memic_operation_type memic_start_addr mlx5_ifc_alloc_memic_in_bits log_memic_addr_alignment range_start_addr range_size memic_size mlx5_ifc_dealloc_memic_in_bits mlx5_sw_icm_type MLX5_SW_ICM_TYPE_STEERING MLX5_SW_ICM_TYPE_HEADER_MODIFY mlx5_ib_mmap_cmd MLX5_IB_MMAP_REGULAR_PAGE MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES MLX5_IB_MMAP_WC_PAGE MLX5_IB_MMAP_NC_PAGE MLX5_IB_MMAP_CORE_CLOCK MLX5_IB_MMAP_ALLOC_WC MLX5_IB_MMAP_CLOCK_INFO MLX5_IB_MMAP_DEVICE_MEM mlx5_ib_dm_methods MLX5_IB_METHOD_DM_MAP_OP_ADDR MLX5_IB_METHOD_DM_QUERY mlx5_ib_dm_map_op_addr_attrs MLX5_IB_ATTR_DM_MAP_OP_ADDR_REQ_HANDLE MLX5_IB_ATTR_DM_MAP_OP_ADDR_REQ_OP MLX5_IB_ATTR_DM_MAP_OP_ADDR_RESP_START_OFFSET MLX5_IB_ATTR_DM_MAP_OP_ADDR_RESP_PAGE_INDEX mlx5_ib_query_dm_attrs MLX5_IB_ATTR_QUERY_DM_REQ_HANDLE MLX5_IB_ATTR_QUERY_DM_RESP_START_OFFSET MLX5_IB_ATTR_QUERY_DM_RESP_PAGE_INDEX MLX5_IB_ATTR_QUERY_DM_RESP_LENGTH mlx5_ib_alloc_dm_attrs MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX MLX5_IB_ATTR_ALLOC_DM_REQ_TYPE mlx5_ib_uapi_dm_type MLX5_IB_UAPI_DM_TYPE_MEMIC MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM MLX5_MEMIC_BASE_ALIGN MLX5_MEMIC_BASE_SIZE mlx5_ib_mmap_type MLX5_IB_MMAP_TYPE_MEMIC MLX5_IB_MMAP_TYPE_VAR MLX5_IB_MMAP_TYPE_UAR_WC MLX5_IB_MMAP_TYPE_UAR_NC MLX5_IB_MMAP_TYPE_MEMIC_OP mlx5_user_mmap_entry rdma_entry mmap_flag page_idx mlx5_ib_dm ibdm mlx5_ib_dm_op_entry mentry op_addr mlx5_ib_dm_memic ops_xa_lock mlx5_ib_dm_icm user_virt ib_qp_create_flags IB_QP_CREATE_IPOIB_UD_LSO IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK IB_QP_CREATE_CROSS_CHANNEL IB_QP_CREATE_MANAGED_SEND IB_QP_CREATE_MANAGED_RECV IB_QP_CREATE_NETIF_QP IB_QP_CREATE_INTEGRITY_EN IB_QP_CREATE_NETDEV_USE IB_QP_CREATE_SCATTER_FCS IB_QP_CREATE_CVLAN_STRIPPING IB_QP_CREATE_SOURCE_QPN IB_QP_CREATE_PCI_WRITE_END_PADDING IB_QP_CREATE_RESERVED_START IB_QP_CREATE_RESERVED_END ib_qp_attr_mask IB_QP_STATE IB_QP_CUR_STATE IB_QP_EN_SQD_ASYNC_NOTIFY IB_QP_ACCESS_FLAGS IB_QP_PKEY_INDEX IB_QP_PORT IB_QP_QKEY IB_QP_AV IB_QP_PATH_MTU IB_QP_TIMEOUT IB_QP_RETRY_CNT IB_QP_RNR_RETRY IB_QP_RQ_PSN IB_QP_MAX_QP_RD_ATOMIC IB_QP_ALT_PATH IB_QP_MIN_RNR_TIMER IB_QP_SQ_PSN IB_QP_MAX_DEST_RD_ATOMIC IB_QP_PATH_MIG_STATE IB_QP_CAP IB_QP_DEST_QPN IB_QP_RESERVED1 IB_QP_RESERVED2 IB_QP_RESERVED3 IB_QP_RESERVED4 IB_QP_RATE_LIMIT IB_QP_ATTR_STANDARD_BITS ib_ud_wr ah remote_qpn remote_qkey MLX5_CAP_PORT_TYPE_IB MLX5_CAP_PORT_TYPE_ETH IFLA_VF_LINK_STATE_AUTO IFLA_VF_LINK_STATE_ENABLE IFLA_VF_LINK_STATE_DISABLE __IFLA_VF_LINK_STATE_MAX MLX5_HCA_VPORT_SEL_PORT_GUID MLX5_HCA_VPORT_SEL_NODE_GUID MLX5_HCA_VPORT_SEL_STATE_POLICY phy_port_state MLX5_AAA_111 mlx5_hca_vport_context sm_virt_aware has_raw port_physical_state cap_mask1 cap_mask1_perm cap_mask2 cap_mask2_perm qkey_violation_counter pkey_violation_counter grh_required ib_port_speed IB_SPEED_SDR IB_SPEED_DDR IB_SPEED_QDR IB_SPEED_FDR10 IB_SPEED_FDR IB_SPEED_EDR IB_SPEED_HDR IB_SPEED_NDR ib_process_mad_flags IB_MAD_IGNORE_MKEY IB_MAD_IGNORE_BKEY IB_MAD_IGNORE_ALL ib_mad_result IB_MAD_RESULT_FAILURE IB_MAD_RESULT_SUCCESS IB_MAD_RESULT_REPLY IB_MAD_RESULT_CONSUMED MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO ib_class_port_info capability_mask cap_mask2_resp_time redirect_gid redirect_tcslfl redirect_lid redirect_pkey redirect_qp redirect_qkey trap_gid trap_tcslfl trap_lid trap_pkey trap_hlqp trap_qkey ib_port_capability_mask_bits IB_PORT_SM IB_PORT_NOTICE_SUP IB_PORT_TRAP_SUP IB_PORT_OPT_IPD_SUP IB_PORT_AUTO_MIGR_SUP IB_PORT_SL_MAP_SUP IB_PORT_MKEY_NVRAM IB_PORT_PKEY_NVRAM IB_PORT_LED_INFO_SUP IB_PORT_SM_DISABLED IB_PORT_SYS_IMAGE_GUID_SUP IB_PORT_PKEY_SW_EXT_PORT_TRAP_SUP IB_PORT_EXTENDED_SPEEDS_SUP IB_PORT_CAP_MASK2_SUP IB_PORT_CM_SUP IB_PORT_SNMP_TUNNEL_SUP IB_PORT_REINIT_SUP IB_PORT_DEVICE_MGMT_SUP IB_PORT_VENDOR_CLASS_SUP IB_PORT_DR_NOTICE_SUP IB_PORT_CAP_MASK_NOTICE_SUP IB_PORT_BOOT_MGMT_SUP IB_PORT_LINK_LATENCY_SUP IB_PORT_CLIENT_REG_SUP IB_PORT_OTHER_LOCAL_CHANGES_SUP IB_PORT_LINK_SPEED_WIDTH_TABLE_SUP IB_PORT_VENDOR_SPECIFIC_MADS_TABLE_SUP IB_PORT_MCAST_PKEY_TRAP_SUPPRESSION_SUP IB_PORT_MCAST_FDB_TOP_SUP IB_PORT_HIERARCHY_INFO_SUP ib_port_capability_mask2_bits IB_PORT_SET_NODE_DESC_SUP IB_PORT_EX_PORT_INFO_EX_SUP IB_PORT_VIRT_SUP IB_PORT_SWITCH_PORT_STATE_TABLE_SUP IB_PORT_LINK_WIDTH_2X_SUP IB_PORT_LINK_SPEED_HDR_SUP IB_PORT_LINK_SPEED_NDR_SUP ib_smp hop_ptr hop_cnt dr_slid dr_dlid initial_path return_path ib_pma_portcounters port_select counter_select port_rcv_remphys_errors vl15_dropped port_xmit_data port_rcv_data port_xmit_packets port_rcv_packets ib_pma_portcounters_ext port_unicast_xmit_packets port_unicast_rcv_packets port_multicast_xmit_packets port_multicast_rcv_packets MLX5_IB_VENDOR_CLASS1 MLX5_IB_VENDOR_CLASS2 RDMA_NODE_IB_CA RDMA_NODE_IB_SWITCH RDMA_NODE_IB_ROUTER RDMA_NODE_RNIC RDMA_NODE_USNIC RDMA_NODE_USNIC_UDP RDMA_NODE_UNSPECIFIED ib_signature_prot_cap IB_PROT_T10DIF_TYPE_1 IB_PROT_T10DIF_TYPE_2 IB_PROT_T10DIF_TYPE_3 ib_signature_guard_cap IB_GUARD_T10DIF_CRC IB_GUARD_T10DIF_CSUM ib_device_cap_flags IB_DEVICE_RESIZE_MAX_WR IB_DEVICE_BAD_PKEY_CNTR IB_DEVICE_BAD_QKEY_CNTR IB_DEVICE_RAW_MULTI IB_DEVICE_AUTO_PATH_MIG IB_DEVICE_CHANGE_PHY_PORT IB_DEVICE_UD_AV_PORT_ENFORCE IB_DEVICE_CURR_QP_STATE_MOD IB_DEVICE_SHUTDOWN_PORT IB_DEVICE_PORT_ACTIVE_EVENT IB_DEVICE_SYS_IMAGE_GUID IB_DEVICE_RC_RNR_NAK_GEN IB_DEVICE_SRQ_RESIZE IB_DEVICE_N_NOTIFY_CQ IB_DEVICE_LOCAL_DMA_LKEY IB_DEVICE_MEM_WINDOW IB_DEVICE_UD_IP_CSUM IB_DEVICE_UD_TSO IB_DEVICE_XRC IB_DEVICE_MEM_MGT_EXTENSIONS IB_DEVICE_BLOCK_MULTICAST_LOOPBACK IB_DEVICE_MEM_WINDOW_TYPE_2A IB_DEVICE_MEM_WINDOW_TYPE_2B IB_DEVICE_RC_IP_CSUM IB_DEVICE_RAW_IP_CSUM IB_DEVICE_CROSS_CHANNEL IB_DEVICE_MANAGED_FLOW_STEERING IB_DEVICE_INTEGRITY_HANDOVER IB_DEVICE_ON_DEMAND_PAGING IB_DEVICE_SG_GAPS_REG IB_DEVICE_VIRTUAL_FUNCTION IB_DEVICE_RAW_SCATTER_FCS IB_DEVICE_RDMA_NETDEV_OPA IB_DEVICE_PCI_WRITE_END_PADDING IB_DEVICE_ALLOW_USER_UNREG ib_odp_general_cap_bits IB_ODP_SUPPORT IB_ODP_SUPPORT_IMPLICIT ib_odp_transport_cap_bits IB_ODP_SUPPORT_SEND IB_ODP_SUPPORT_RECV IB_ODP_SUPPORT_WRITE IB_ODP_SUPPORT_READ IB_ODP_SUPPORT_ATOMIC IB_ODP_SUPPORT_SRQ_RECV ib_tm_cap_flags IB_TM_CAP_RNDV_RC ib_port_phys_state IB_PORT_PHYS_STATE_SLEEP IB_PORT_PHYS_STATE_POLLING IB_PORT_PHYS_STATE_DISABLED IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING IB_PORT_PHYS_STATE_LINK_UP IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY IB_PORT_PHYS_STATE_PHY_TEST ib_port_width IB_WIDTH_1X IB_WIDTH_2X IB_WIDTH_4X IB_WIDTH_8X IB_WIDTH_12X ib_device_modify_flags IB_DEVICE_MODIFY_SYS_IMAGE_GUID IB_DEVICE_MODIFY_NODE_DESC ib_raw_packet_caps IB_RAW_PACKET_CAP_CVLAN_STRIPPING IB_RAW_PACKET_CAP_SCATTER_FCS IB_RAW_PACKET_CAP_IP_CSUM IB_RAW_PACKET_CAP_DELAY_DROP IB_LRH_BYTES IB_ETH_BYTES IB_VLAN_BYTES IB_GRH_BYTES IB_IP4_BYTES IB_UDP_BYTES IB_BTH_BYTES IB_DETH_BYTES IB_EXT_ATOMICETH_BYTES IB_EXT_XRC_BYTES IB_ICRC_BYTES MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q mlx5_ifc_qos_cap_bits packet_pacing esw_scheduling esw_bw_share esw_rate_limit packet_pacing_burst_bound packet_pacing_typical_size reserved_at_7 nic_sq_scheduling nic_bw_share nic_rate_limit packet_pacing_uid log_esw_max_sched_depth log_max_qos_nic_queue_group packet_pacing_max_rate packet_pacing_min_rate packet_pacing_rate_table_size esw_element_type esw_tsar_type max_qos_para_vport max_tsar_bw_share nic_element_type nic_tsar_type log_meter_aso_granularity reserved_at_128 log_meter_aso_max_alloc log_max_num_meter_aso reserved_at_138 mlx5_ifc_per_protocol_networking_offload_caps_bits csum_cap vlan_cap lro_cap lro_psh_flag lro_time_stamp reserved_at_5 wqe_vlan_insert self_lb_en_modifiable max_lso_cap multi_pkt_send_wqe wqe_inline_mode rss_ind_tbl_cap reg_umr_sq scatter_fcs enhanced_multi_pkt_send_wqe tunnel_lso_const_out_ip_id tunnel_lro_gre tunnel_lro_vxlan tunnel_stateless_gre tunnel_stateless_vxlan swp_csum swp_lso cqe_checksum_full tunnel_stateless_geneve_tx tunnel_stateless_mpls_over_udp tunnel_stateless_mpls_over_gre tunnel_stateless_vxlan_gpe tunnel_stateless_ipv4_over_vxlan tunnel_stateless_ip_over_ip insert_trailer tunnel_stateless_ip_over_ip_rx tunnel_stateless_ip_over_ip_tx reserved_at_2e max_vxlan_udp_ports reserved_at_38 max_geneve_opt_len tunnel_stateless_geneve_rx lro_min_mss_size lro_timer_supported_periods MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME mlx5_ifc_roce_cap_bits roce_apm sw_r_roce_src_udp_port fl_rc_qp_when_roce_enabled qp_ts_format l3_type reserved_at_90 roce_version r_roce_dest_udp_port r_roce_max_src_udp_port r_roce_min_src_udp_port roce_address_table_size mlx5_ifc_virtio_emulation_cap_bits desc_tunnel_offload_type eth_frame_offload_type virtio_version_1_0 device_features_bits_mask event_mode virtio_queue_type max_tunnel_desc log_doorbell_stride log_doorbell_bar_size doorbell_bar_offset max_emulated_devices max_num_virtio_queues umem_1_buffer_param_a umem_1_buffer_param_b umem_2_buffer_param_a umem_2_buffer_param_b umem_3_buffer_param_a umem_3_buffer_param_b mlx5_ifc_atomic_caps_bits atomic_req_8B_endianness_mode supported_atomic_req_8B_endianness_mode_1 atomic_operations atomic_size_qp atomic_size_dc MLX5_CAP_UMR_FENCE_STRONG MLX5_CAP_UMR_FENCE_SMALL MLX5_CAP_UMR_FENCE_NONE mlx5_ifc_alloc_pd_out_bits mlx5_ifc_alloc_pd_in_bits mlx5_ifc_ptys_reg_bits an_disable_admin an_disable_cap proto_mask an_status reserved_at_24 data_rate_oper ext_eth_proto_capability eth_proto_capability ib_link_width_capability ib_proto_capability ext_eth_proto_admin eth_proto_admin ib_link_width_admin ib_proto_admin ext_eth_proto_oper eth_proto_oper ib_link_width_oper ib_proto_oper connector_type eth_proto_lp_advertise reserved_at_1a0 MLX5_MIN_PKEY_TABLE_SIZE MLX5_MAX_LOG_PKEY_TABLE MLX5_BFREGS_PER_UAR MLX5_MAX_UARS MLX5_NON_FP_BFREGS_PER_UAR MLX5_FP_BFREGS_PER_UAR MLX5_MAX_BFREGS MLX5_UARS_IN_PAGE MLX5_NON_FP_BFREGS_IN_PAGE MLX5_MIN_DYN_BFREGS MLX5_MAX_DYN_BFREGS MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT MLX5_PORT_CHANGE_SUBTYPE_DOWN MLX5_PORT_CHANGE_SUBTYPE_ACTIVE MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED MLX5_PORT_CHANGE_SUBTYPE_LID MLX5_PORT_CHANGE_SUBTYPE_PKEY MLX5_PORT_CHANGE_SUBTYPE_GUID MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG MLX5_ROCE_VERSION_1_CAP MLX5_ROCE_VERSION_2_CAP MLX5_ROCE_L3_TYPE_IPV4 MLX5_ROCE_L3_TYPE_IPV6 MLX5_ROCE_L3_TYPE_IPV4_CAP MLX5_ROCE_L3_TYPE_IPV6_CAP MLX5_MAX_SGE_RD MLX5_ATOMIC_OPS_CMP_SWAP MLX5_ATOMIC_OPS_FETCH_ADD MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD mlx5_dev_event MLX5_DEV_EVENT_SYS_ERROR MLX5_DEV_EVENT_PORT_AFFINITY MLX5_PTYS_IB MLX5_PTYS_EN mlx5e_link_mode MLX5E_1000BASE_CX_SGMII MLX5E_1000BASE_KX MLX5E_10GBASE_CX4 MLX5E_10GBASE_KX4 MLX5E_10GBASE_KR MLX5E_20GBASE_KR2 MLX5E_40GBASE_CR4 MLX5E_40GBASE_KR4 MLX5E_56GBASE_R4 MLX5E_10GBASE_CR MLX5E_10GBASE_SR MLX5E_10GBASE_ER MLX5E_40GBASE_SR4 MLX5E_40GBASE_LR4 MLX5E_50GBASE_SR2 MLX5E_100GBASE_CR4 MLX5E_100GBASE_SR4 MLX5E_100GBASE_KR4 MLX5E_100GBASE_LR4 MLX5E_100BASE_TX MLX5E_1000BASE_T MLX5E_10GBASE_T MLX5E_25GBASE_CR MLX5E_25GBASE_KR MLX5E_25GBASE_SR MLX5E_50GBASE_CR2 MLX5E_50GBASE_KR2 MLX5E_LINK_MODES_NUMBER mlx5e_ext_link_mode MLX5E_SGMII_100M MLX5E_1000BASE_X_SGMII MLX5E_5GBASE_R MLX5E_10GBASE_XFI_XAUI_1 MLX5E_40GBASE_XLAUI_4_XLPPI_4 MLX5E_25GAUI_1_25GBASE_CR_KR MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR MLX5E_CAUI_4_100GBASE_CR4_KR4 MLX5E_100GAUI_2_100GBASE_CR2_KR2 MLX5E_100GAUI_1_100GBASE_CR_KR MLX5E_200GAUI_4_200GBASE_CR4_KR4 MLX5E_200GAUI_2_200GBASE_CR2_KR2 MLX5E_400GAUI_8 MLX5E_400GAUI_4_400GBASE_CR4_KR4 MLX5E_EXT_LINK_MODES_NUMBER mlx5_ptys_width MLX5_PTYS_WIDTH_1X MLX5_PTYS_WIDTH_2X MLX5_PTYS_WIDTH_4X MLX5_PTYS_WIDTH_8X MLX5_PTYS_WIDTH_12X MLX5_VPORT_PF MLX5_VPORT_FIRST_VF MLX5_VPORT_ECPF MLX5_VPORT_UPLINK mlx5_flow_namespace_type MLX5_FLOW_NAMESPACE_BYPASS MLX5_FLOW_NAMESPACE_LAG MLX5_FLOW_NAMESPACE_OFFLOADS MLX5_FLOW_NAMESPACE_ETHTOOL MLX5_FLOW_NAMESPACE_KERNEL MLX5_FLOW_NAMESPACE_LEFTOVERS MLX5_FLOW_NAMESPACE_ANCHOR MLX5_FLOW_NAMESPACE_FDB MLX5_FLOW_NAMESPACE_ESW_EGRESS MLX5_FLOW_NAMESPACE_ESW_INGRESS MLX5_FLOW_NAMESPACE_SNIFFER_RX MLX5_FLOW_NAMESPACE_SNIFFER_TX MLX5_FLOW_NAMESPACE_EGRESS MLX5_FLOW_NAMESPACE_EGRESS_KERNEL MLX5_FLOW_NAMESPACE_RDMA_RX MLX5_FLOW_NAMESPACE_RDMA_RX_KERNEL MLX5_FLOW_NAMESPACE_RDMA_TX MLX5_FLOW_NAMESPACE_RDMA_RX_COUNTERS MLX5_FLOW_NAMESPACE_RDMA_TX_COUNTERS rdma_lag_flags RDMA_LAG_FLAGS_HASH_ALL_SLAVES MLX5_FENCE_MODE_NONE MLX5_FENCE_MODE_INITIATOR_SMALL MLX5_FENCE_MODE_FENCE MLX5_FENCE_MODE_STRONG_ORDERING MLX5_FENCE_MODE_SMALL_AND_FENCE mlx5_lib_caps MLX5_LIB_CAP_4K_UAR MLX5_LIB_CAP_DYN_UAR mlx5_ib_alloc_uctx_v2_flags MLX5_IB_ALLOC_UCTX_DEVX mlx5_ib_alloc_ucontext_req_v2 comp_mask max_cqe_version mlx5_ib_alloc_ucontext_resp_mask MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG mlx5_user_cmds_supp_uhw MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE MLX5_USER_CMDS_SUPP_UHW_CREATE_AH MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN mlx5_ib_alloc_ucontext_resp qp_tab_size bf_reg_size tot_bfregs max_sq_desc_sz max_rq_desc_sz max_send_wqebb max_srq_recv_wr flow_action_flags cmds_supp_uhw eth_min_inline clock_info_versions hca_core_clock_offset log_uar_size num_uars_per_page mlx5_ib_alloc_pd_resp mlx5_ib_tso_caps max_tso mlx5_ib_rss_caps rx_hash_fields_mask rx_hash_function mlx5_ib_cqe_comp_caps max_num supported_format mlx5_ib_packet_pacing_cap_flags MLX5_IB_PP_SUPPORT_BURST mlx5_packet_pacing_caps qp_rate_limit_min qp_rate_limit_max cap_flags mlx5_ib_mpw_caps MPW_RESERVED MLX5_IB_ALLOW_MPW MLX5_IB_SUPPORT_EMPW mlx5_ib_sw_parsing_offloads MLX5_IB_SW_PARSING MLX5_IB_SW_PARSING_CSUM MLX5_IB_SW_PARSING_LSO mlx5_ib_sw_parsing_caps sw_parsing_offloads mlx5_ib_striding_rq_caps min_single_stride_log_num_of_bytes max_single_stride_log_num_of_bytes min_single_wqe_log_num_of_strides max_single_wqe_log_num_of_strides mlx5_ib_dci_streams_caps max_log_num_concurent max_log_num_errored mlx5_ib_query_dev_resp_flags MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT mlx5_ib_tunnel_offloads MLX5_IB_TUNNELED_OFFLOADS_VXLAN MLX5_IB_TUNNELED_OFFLOADS_GRE MLX5_IB_TUNNELED_OFFLOADS_GENEVE MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP mlx5_ib_query_device_resp tso_caps cqe_comp_caps packet_pacing_caps mlx5_ib_support_multi_pkt_send_wqes sw_parsing_caps striding_rq_caps tunnel_offloads_caps dci_streams_caps mlx5_rx_hash_function_flags MLX5_RX_HASH_FUNC_TOEPLITZ mlx5_rx_hash_fields MLX5_RX_HASH_SRC_IPV4 MLX5_RX_HASH_DST_IPV4 MLX5_RX_HASH_SRC_IPV6 MLX5_RX_HASH_DST_IPV6 MLX5_RX_HASH_SRC_PORT_TCP MLX5_RX_HASH_DST_PORT_TCP MLX5_RX_HASH_SRC_PORT_UDP MLX5_RX_HASH_DST_PORT_UDP MLX5_RX_HASH_IPSEC_SPI MLX5_RX_HASH_INNER MLX5_IB_CLOCK_INFO_V1 uverbs_obj_idr_type destroy_object uverbs_methods_device UVERBS_METHOD_INVOKE_WRITE UVERBS_METHOD_INFO_HANDLES UVERBS_METHOD_QUERY_PORT UVERBS_METHOD_GET_CONTEXT UVERBS_METHOD_QUERY_CONTEXT UVERBS_METHOD_QUERY_GID_TABLE UVERBS_METHOD_QUERY_GID_ENTRY uverbs_methods_actions_flow_action_ops UVERBS_METHOD_FLOW_ACTION_ESP_CREATE UVERBS_METHOD_FLOW_ACTION_DESTROY UVERBS_METHOD_FLOW_ACTION_ESP_MODIFY uapi_definition_scope UAPI_SCOPE_OBJECT UAPI_SCOPE_METHOD mlx5_ib_create_flow_action_attrs MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS mlx5_ib_var_alloc_attrs MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID mlx5_ib_var_obj_destroy_attrs MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE mlx5_ib_var_obj_methods MLX5_IB_METHOD_VAR_OBJ_ALLOC MLX5_IB_METHOD_VAR_OBJ_DESTROY mlx5_ib_uar_alloc_attrs MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID mlx5_ib_uar_obj_destroy_attrs MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE mlx5_ib_uar_obj_methods MLX5_IB_METHOD_UAR_OBJ_ALLOC MLX5_IB_METHOD_UAR_OBJ_DESTROY mlx5_ib_objects MLX5_IB_OBJECT_DEVX MLX5_IB_OBJECT_DEVX_OBJ MLX5_IB_OBJECT_DEVX_UMEM MLX5_IB_OBJECT_FLOW_MATCHER MLX5_IB_OBJECT_DEVX_ASYNC_CMD_FD MLX5_IB_OBJECT_DEVX_ASYNC_EVENT_FD MLX5_IB_OBJECT_VAR MLX5_IB_OBJECT_PP MLX5_IB_OBJECT_UAR mlx5_ib_device_query_context_attrs MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX mlx5_ib_uapi_uar_alloc_type MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC MLX5_IB_MMAP_OFFSET_START MLX5_IB_MMAP_OFFSET_END MLX5_IB_MMAP_CMD_SHIFT MLX5_IB_MMAP_CMD_MASK MLX5_TM_MAX_RNDV_MSG_SIZE MLX5_TM_MAX_SGE MLX5_IB_INVALID_UAR_INDEX MLX5_IB_INVALID_BFREG mlx5_ib_pd ibpd mlx5_ib_rwq_ind_table ib_rwq_ind_tbl mlx5_ib_xrcd ibxrcd mlx5_ib_mw ibmw mmkey MLX5_MAX_DELAY_DROP_TIMEOUT_MS mlx5_accel_ipsec_cap MLX5_ACCEL_IPSEC_CAP_DEVICE MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA MLX5_ACCEL_IPSEC_CAP_ESP MLX5_ACCEL_IPSEC_CAP_IPV6 MLX5_ACCEL_IPSEC_CAP_LSO MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER MLX5_ACCEL_IPSEC_CAP_ESN MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN mlx5_ib_event_work is_slave MLX5_ATOMIC_SIZE_QP_8BYTES MLX5_VPORT_ACCESS_METHOD_MAD MLX5_VPORT_ACCESS_METHOD_HCA MLX5_VPORT_ACCESS_METHOD_NIC mlx5_reg_node_desc ib_max_vl_num __IB_MAX_VL_0 __IB_MAX_VL_0_1 __IB_MAX_VL_0_3 __IB_MAX_VL_0_7 __IB_MAX_VL_0_14 mlx5_vl_hw_cap MLX5_VL_HW_0 MLX5_VL_HW_0_1 MLX5_VL_HW_0_2 MLX5_VL_HW_0_3 MLX5_VL_HW_0_4 MLX5_VL_HW_0_5 MLX5_VL_HW_0_6 MLX5_VL_HW_0_7 MLX5_VL_HW_0_14 MAX_UMR_WR mlx5_flow_namespace ib_block_iter __sg __dma_addr __sg_numblocks __sg_nents __sg_advance __pg_bit MLX5_WQE_CTRL_CQ_UPDATE MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE MLX5_WQE_CTRL_SOLICITED MLX5_SEND_WQE_DS MLX5_SEND_WQE_BB MLX5_RCV_DBR MLX5_SND_DBR general_id umr_mkey tis_tir_num mlx5_wqe_ctrl_seg opmod_idx_opcode qpn_ds fm_ce_se ib_mr_status_check IB_MR_CHECK_SIG_STATUS ib_send_flags IB_SEND_FENCE IB_SEND_SIGNALED IB_SEND_SOLICITED IB_SEND_INLINE IB_SEND_IP_CSUM IB_SEND_RESERVED_START IB_SEND_RESERVED_END ib_mr_rereg_flags IB_MR_REREG_TRANS IB_MR_REREG_PD IB_MR_REREG_ACCESS IB_MR_REREG_SUPPORTED ib_odp_counters invalidations ib_umem_dmabuf first_sg first_sg_offset last_sg_trim umem_invalidate_func_t ib_peer_mem_flags IB_PEER_MEM_ALLOW IB_PEER_MEM_INVAL_SUPP ib_umem_odp umem_mutex is_implicit_odp MLX5_MKC_ACCESS_MODE_PA MLX5_MKC_ACCESS_MODE_MTT MLX5_MKC_ACCESS_MODE_KLMS MLX5_MKC_ACCESS_MODE_KSM MLX5_MKC_ACCESS_MODE_SW_ICM MLX5_MKC_ACCESS_MODE_MEMIC mlx5_ifc_mkc_bits access_mode_4_2 reserved_at_6 reserved_at_e small_fence_on_rdma_read_response umr_en access_mode_1_0 ma_translation_mode reserved_at_1c mkey_7_0 length64 bsf_en sync_umr reserved_at_63 expected_sigerr_count reserved_at_66 en_rinval bsf_octword_size translations_octword_size reserved_at_1d9 reserved_at_1e0 mlx5_ifc_create_mkey_out_bits mkey_index mlx5_ifc_create_mkey_in_bits pg_access mkey_umem_valid reserved_at_62 memory_key_mkey_entry translations_octword_actual_size klm_pas_mtt MLX5_EN_RD MLX5_EN_WR MLX5_MKEY_MR MLX5_MKEY_MW MLX5_MKEY_INDIRECT_DEVX MLX5_PROF_MASK_QP_SIZE MLX5_PROF_MASK_MR_CACHE mlx5_async_cbk_t mlx5_async_work mlx5_mtt ptag mlx5_klm bcount mlx5_ib_alloc_mw num_klms mlx5_umr_wr xlt_size ignore_free_state mlx5_ib_mtt_access_flags MLX5_IB_MTT_READ MLX5_IB_MTT_WRITE cb_work descs_alloc desc_map max_descs pi_mr klm_mr mtt_mr data_iova pi_iova meta_ndescs mlx5_ib_mr ibmr cache_ent implicit_children odp_destroy odp_stats is_odp_implicit mlx5_ib_umr_context MAX_PENDING_REG_MR ib_rate IB_RATE_PORT_CURRENT IB_RATE_2_5_GBPS IB_RATE_5_GBPS IB_RATE_10_GBPS IB_RATE_20_GBPS IB_RATE_30_GBPS IB_RATE_40_GBPS IB_RATE_60_GBPS IB_RATE_80_GBPS IB_RATE_120_GBPS IB_RATE_14_GBPS IB_RATE_56_GBPS IB_RATE_112_GBPS IB_RATE_168_GBPS IB_RATE_25_GBPS IB_RATE_100_GBPS IB_RATE_200_GBPS IB_RATE_300_GBPS IB_RATE_28_GBPS IB_RATE_50_GBPS IB_RATE_400_GBPS IB_RATE_600_GBPS ib_rdma_wr remote_addr ib_wq_flags IB_WQ_FLAGS_CVLAN_STRIPPING IB_WQ_FLAGS_SCATTER_FCS IB_WQ_FLAGS_DELAY_DROP IB_WQ_FLAGS_PCI_WRITE_END_PADDING ib_wq_attr_mask IB_WQ_STATE IB_WQ_CUR_STATE IB_WQ_FLAGS mlx5_ifc_cmd_pas_bits pa_h pa_l reserved_at_34 mlx5_ifc_ads_bits free_ar mlid ack_timeout reserved_at_45 src_addr_index stat_rate rgid_rip f_dscp f_ecn reserved_at_106 f_eth_prio dei_cfi eth_prio vhca_port_num rmac_47_32 rmac_31_0 MLX5_WQ_TYPE_LINKED_LIST MLX5_WQ_TYPE_CYCLIC MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ MLX5_WQ_END_PAD_MODE_NONE MLX5_WQ_END_PAD_MODE_ALIGN mlx5_ifc_rx_hash_field_select_bits l3_prot_type l4_prot_type selected_fields mlx5_ifc_wq_bits end_padding_mode cd_slave hds_skip_first_sge log2_hds_buf_size lwm hw_counter sw_counter log_wq_stride log_wq_pg_sz reserved_at_118 log_wq_sz wq_umem_valid reserved_at_122 log_hairpin_num_packets log_hairpin_data_sz log_wqe_num_of_strides two_byte_shift_en reserved_at_139 log_wqe_stride_size mlx5_ifc_rq_num_bits rq_num MLX5_QPC_OFFLOAD_TYPE_RNDV MLX5_TIMESTAMP_FORMAT_FREE_RUNNING MLX5_TIMESTAMP_FORMAT_DEFAULT MLX5_TIMESTAMP_FORMAT_REAL_TIME mlx5_ifc_qpc_bits isolate_vl_tc reserved_at_15 req_e2e_credit_mode offload_type atomic_like_write_en latency_sensitive reserved_at_26 log_msg_max reserved_at_48 log_rq_size log_rq_stride no_sq log_sq_size ts_format rlky ulp_stateless_offload_mode primary_address_path secondary_address_path log_ack_req_freq reserved_at_384 log_sra_max reserved_at_38b retry_count reserved_at_393 fre cur_rnr_retry cur_retry_count reserved_at_39b reserved_at_3a0 reserved_at_3c0 next_send_psn reserved_at_3e0 log_num_dci_stream_channels cqn_snd log_num_dci_errored_streams deth_sqpn reserved_at_420 reserved_at_440 last_acked_psn log_rra_max reserved_at_48b atomic_mode rre rwe rae reserved_at_493 reserved_at_49a cd_slave_receive cd_slave_send cd_master min_rnr_nak next_rcv_psn reserved_at_4e0 cqn_rcv q_key reserved_at_560 rq_type srqn_rmpn_xrqn rmsn hw_sq_wqebb_counter sw_sq_wqebb_counter hw_rq_counter sw_rq_counter reserved_at_600 reserved_at_620 cgs cs_req cs_res dc_access_key reserved_at_680 reserved_at_684 mlx5_ifc_tisc_bits strict_lag_tx_port_affinity tls_en MLX5_TIRC_DISP_TYPE_DIRECT MLX5_TIRC_DISP_TYPE_INDIRECT MLX5_RX_HASH_FN_NONE MLX5_RX_HASH_FN_INVERTED_XOR8 MLX5_RX_HASH_FN_TOEPLITZ MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST mlx5_ifc_tirc_bits disp_type reserved_at_25 lro_timeout_period_usecs packet_merge_mask lro_max_ip_payload_size inline_rqn rx_hash_symmetric reserved_at_101 tunneled_offload_en reserved_at_103 indirect_table rx_hash_fn reserved_at_124 self_lb_block rx_hash_toeplitz_key rx_hash_field_selector_outer rx_hash_field_selector_inner reserved_at_2c0 mlx5_ifc_sqc_bits flush_in_error_en allow_multi_pkt_send_wqe min_wqe_inline_mode reg_umr allow_swp reserved_at_f hairpin_peer_rq hairpin_peer_vhca packet_pacing_rate_limit_index tis_lst_sz qos_queue_group_id tis_num_0 mlx5_ifc_rqtc_bits list_q_type reserved_at_a8 rqt_max_size rq_vhca_id_format rqt_actual_size MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP mlx5_ifc_rqc_bits delay_drop_en vsd mem_rq_type reserved_at_68 rmpn hairpin_peer_sq mlx5_ifc_dctc_bits reserved_at_98 srqn_xrqn reserved_at_e8 my_addr_index reserved_at_170 dc_access_key_violation_count mlx5_ifc_rts2rts_qp_in_bits opt_param_mask qpc reserved_at_800 mlx5_ifc_modify_tis_bitmask_bits mlx5_ifc_modify_tis_in_bits mlx5_ifc_modify_sq_in_bits sq_state reserved_at_44 sqn modify_bitmask MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID mlx5_ifc_modify_rq_in_bits rq_state rqn mlx5_ifc_create_tis_in_bits mlx5_ifc_create_tir_out_bits icm_address_63_40 icm_address_39_32 icm_address_31_0 mlx5_ifc_create_tir_in_bits mlx5_ifc_create_sq_in_bits mlx5_ifc_create_rqt_in_bits rqt_context mlx5_ifc_create_rq_in_bits mlx5_ifc_create_qp_out_bits mlx5_ifc_create_qp_in_bits input_qpn reserved_at_861 mlx5_ifc_create_dct_out_bits mlx5_ifc_create_dct_in_bits dct_context_entry MLX5_STAT_RATE_OFFSET MLX5_L3_PROT_TYPE_IPV4 MLX5_L3_PROT_TYPE_IPV6 MLX5_L4_PROT_TYPE_TCP MLX5_L4_PROT_TYPE_UDP MLX5_HASH_FIELD_SEL_SRC_IP MLX5_HASH_FIELD_SEL_DST_IP MLX5_HASH_FIELD_SEL_L4_SPORT MLX5_HASH_FIELD_SEL_L4_DPORT MLX5_HASH_FIELD_SEL_IPSEC_SPI MLX5_ATOMIC_MODE_OFFSET MLX5_ATOMIC_MODE_IB_COMP MLX5_ATOMIC_MODE_CX MLX5_ATOMIC_MODE_8B MLX5_ATOMIC_MODE_16B MLX5_ATOMIC_MODE_32B MLX5_ATOMIC_MODE_64B MLX5_ATOMIC_MODE_128B MLX5_ATOMIC_MODE_256B mlx5_qp_optpar MLX5_QP_OPTPAR_ALT_ADDR_PATH MLX5_QP_OPTPAR_RRE MLX5_QP_OPTPAR_RAE MLX5_QP_OPTPAR_RWE MLX5_QP_OPTPAR_PKEY_INDEX MLX5_QP_OPTPAR_Q_KEY MLX5_QP_OPTPAR_RNR_TIMEOUT MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH MLX5_QP_OPTPAR_SRA_MAX MLX5_QP_OPTPAR_RRA_MAX MLX5_QP_OPTPAR_PM_STATE MLX5_QP_OPTPAR_RETRY_COUNT MLX5_QP_OPTPAR_RNR_RETRY MLX5_QP_OPTPAR_ACK_TIMEOUT MLX5_QP_OPTPAR_LAG_TX_AFF MLX5_QP_OPTPAR_PRI_PORT MLX5_QP_OPTPAR_SRQN MLX5_QP_OPTPAR_CQN_RCV MLX5_QP_OPTPAR_DC_HS MLX5_QP_OPTPAR_DC_KEY MLX5_QP_OPTPAR_COUNTER_SET_ID mlx5_qp_state MLX5_QP_STATE_RST MLX5_QP_STATE_INIT MLX5_QP_STATE_RTR MLX5_QP_STATE_RTS MLX5_QP_STATE_SQER MLX5_QP_STATE_SQD MLX5_QP_STATE_ERR MLX5_QP_STATE_SQ_DRAINING MLX5_QP_STATE_SUSPENDED MLX5_QP_NUM_STATE MLX5_QP_STATE MLX5_QP_STATE_BAD MLX5_SQ_STATE_NA MLX5_SQ_NUM_STATE MLX5_RQ_STATE_NA MLX5_RQ_NUM_STATE MLX5_QP_ST_RC MLX5_QP_ST_UC MLX5_QP_ST_UD MLX5_QP_ST_XRC MLX5_QP_ST_MLX MLX5_QP_ST_DCI MLX5_QP_ST_DCT MLX5_QP_ST_QP0 MLX5_QP_ST_QP1 MLX5_QP_ST_RAW_ETHERTYPE MLX5_QP_ST_RAW_IPV6 MLX5_QP_ST_SNIFFER MLX5_QP_ST_SYNC_UMR MLX5_QP_ST_PTP_1588 MLX5_QP_ST_REG_UMR MLX5_QP_ST_MAX MLX5_QP_PM_MIGRATED MLX5_QP_PM_ARMED MLX5_QP_PM_REARM MLX5_NON_ZERO_RQ MLX5_SRQ_RQ MLX5_CRQ_RQ MLX5_ZERO_LEN_RQ MLX5_QP_FLAG_SIGNATURE MLX5_QP_FLAG_SCATTER_CQE MLX5_QP_FLAG_TUNNEL_OFFLOADS MLX5_QP_FLAG_BFREG_INDEX MLX5_QP_FLAG_TYPE_DCT MLX5_QP_FLAG_TYPE_DCI MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC MLX5_QP_FLAG_ALLOW_SCATTER_CQE MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE MLX5_QP_FLAG_UAR_PAGE_INDEX MLX5_QP_FLAG_DCI_STREAM MLX5_WQ_FLAG_SIGNATURE mlx5_ib_create_qp_dci_streams log_num_concurent log_num_errored sq_buf_addr access_key mlx5_ib_create_qp sq_wqe_count rq_wqe_count rq_wqe_shift uidx bfreg_index ece_options dci_streams mlx5_ib_create_qp_rss rx_key_len rx_hash_key mlx5_ib_create_qp_resp_mask MLX5_IB_CREATE_QP_RESP_MASK_TIRN MLX5_IB_CREATE_QP_RESP_MASK_TISN MLX5_IB_CREATE_QP_RESP_MASK_RQN MLX5_IB_CREATE_QP_RESP_MASK_SQN MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR mlx5_ib_create_qp_resp tir_icm_addr mlx5_ib_create_wq_mask MLX5_IB_CREATE_WQ_STRIDING_RQ mlx5_ib_create_wq single_stride_log_num_of_bytes single_wqe_log_num_of_strides mlx5_ib_burst_info mlx5_ib_modify_qp burst_info mlx5_ib_modify_qp_resp mlx5_ib_create_wq_resp mlx5_ib_create_rwq_ind_tbl_resp mlx5_ib_modify_wq MLX5_RES_SCAT_DATA32_CQE MLX5_RES_SCAT_DATA64_CQE MLX5_REQ_SCAT_DATA32_CQE MLX5_REQ_SCAT_DATA64_CQE MLX5_CQE_VERSION_V0 MLX5_CQE_VERSION_V1 mlx5_ib_rq_flags MLX5_IB_RQ_CVLAN_STRIPPING MLX5_IB_RQ_PCI_WRITE_END_PADDING mlx5_ib_wq_flags MLX5_IB_WQ_FLAGS_DELAY_DROP MLX5_IB_WQ_FLAGS_STRIDING_RQ mlx5_ib_rwq ibwq core_qp rq_num_pas rq_page_offset log_num_strides wqe_count MLX5_IB_SQ_UMR_INLINE_THRESHOLD MLX5_IB_ACK_REQ_FREQ raw_qp_set_mask_map MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID MLX5_RAW_QP_RATE_LIMIT mlx5_modify_raw_qp_param rq_q_ctr_id NUM_NON_BLUE_FLAME_BFREGS mlx5_create_qp_params ucmd_size is_rss_raw MLX5_PATH_FLAG_FL MLX5_PATH_FLAG_FREE_AR MLX5_PATH_FLAG_COUNTER mlx5_ib_drain_cqe mlx5_ifc_sqerr2rts_qp_in_bits mlx5_ifc_sqd2rts_qp_in_bits mlx5_ifc_rts2rts_qp_out_bits mlx5_ifc_rtr2rts_qp_out_bits mlx5_ifc_rtr2rts_qp_in_bits mlx5_ifc_rst2init_qp_out_bits mlx5_ifc_rst2init_qp_in_bits mlx5_ifc_query_qp_in_bits mlx5_ifc_query_dct_in_bits mlx5_ifc_qp_2rst_in_bits mlx5_ifc_qp_2err_in_bits mlx5_ifc_init2rtr_qp_out_bits mlx5_ifc_init2rtr_qp_in_bits mlx5_ifc_init2init_qp_out_bits mlx5_ifc_init2init_qp_in_bits mlx5_ifc_drain_dct_in_bits mlx5_ifc_destroy_sq_in_bits mlx5_ifc_destroy_rq_in_bits mlx5_ifc_set_delay_drop_params_in_bits delay_drop_timeout mlx5_ifc_destroy_qp_in_bits mlx5_ifc_destroy_dct_in_bits mlx5_ifc_create_sq_out_bits mbox_info rdma_nldev_attr RDMA_NLDEV_ATTR_UNSPEC RDMA_NLDEV_ATTR_PAD RDMA_NLDEV_ATTR_DEV_INDEX RDMA_NLDEV_ATTR_DEV_NAME RDMA_NLDEV_ATTR_PORT_INDEX RDMA_NLDEV_ATTR_CAP_FLAGS RDMA_NLDEV_ATTR_FW_VERSION RDMA_NLDEV_ATTR_NODE_GUID RDMA_NLDEV_ATTR_SYS_IMAGE_GUID RDMA_NLDEV_ATTR_SUBNET_PREFIX RDMA_NLDEV_ATTR_LID RDMA_NLDEV_ATTR_SM_LID RDMA_NLDEV_ATTR_LMC RDMA_NLDEV_ATTR_PORT_STATE RDMA_NLDEV_ATTR_PORT_PHYS_STATE RDMA_NLDEV_ATTR_DEV_NODE_TYPE RDMA_NLDEV_ATTR_RES_SUMMARY RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_NAME RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_CURR RDMA_NLDEV_ATTR_RES_QP RDMA_NLDEV_ATTR_RES_QP_ENTRY RDMA_NLDEV_ATTR_RES_LQPN RDMA_NLDEV_ATTR_RES_RQPN RDMA_NLDEV_ATTR_RES_RQ_PSN RDMA_NLDEV_ATTR_RES_SQ_PSN RDMA_NLDEV_ATTR_RES_PATH_MIG_STATE RDMA_NLDEV_ATTR_RES_TYPE RDMA_NLDEV_ATTR_RES_STATE RDMA_NLDEV_ATTR_RES_PID RDMA_NLDEV_ATTR_RES_KERN_NAME RDMA_NLDEV_ATTR_RES_CM_ID RDMA_NLDEV_ATTR_RES_CM_ID_ENTRY RDMA_NLDEV_ATTR_RES_PS RDMA_NLDEV_ATTR_RES_SRC_ADDR RDMA_NLDEV_ATTR_RES_DST_ADDR RDMA_NLDEV_ATTR_RES_CQ RDMA_NLDEV_ATTR_RES_CQ_ENTRY RDMA_NLDEV_ATTR_RES_CQE RDMA_NLDEV_ATTR_RES_USECNT RDMA_NLDEV_ATTR_RES_POLL_CTX RDMA_NLDEV_ATTR_RES_MR RDMA_NLDEV_ATTR_RES_MR_ENTRY RDMA_NLDEV_ATTR_RES_RKEY RDMA_NLDEV_ATTR_RES_LKEY RDMA_NLDEV_ATTR_RES_IOVA RDMA_NLDEV_ATTR_RES_MRLEN RDMA_NLDEV_ATTR_RES_PD RDMA_NLDEV_ATTR_RES_PD_ENTRY RDMA_NLDEV_ATTR_RES_LOCAL_DMA_LKEY RDMA_NLDEV_ATTR_RES_UNSAFE_GLOBAL_RKEY RDMA_NLDEV_ATTR_NDEV_INDEX RDMA_NLDEV_ATTR_NDEV_NAME RDMA_NLDEV_ATTR_DRIVER RDMA_NLDEV_ATTR_DRIVER_ENTRY RDMA_NLDEV_ATTR_DRIVER_STRING RDMA_NLDEV_ATTR_DRIVER_PRINT_TYPE RDMA_NLDEV_ATTR_DRIVER_S32 RDMA_NLDEV_ATTR_DRIVER_U32 RDMA_NLDEV_ATTR_DRIVER_S64 RDMA_NLDEV_ATTR_DRIVER_U64 RDMA_NLDEV_ATTR_RES_PDN RDMA_NLDEV_ATTR_RES_CQN RDMA_NLDEV_ATTR_RES_MRN RDMA_NLDEV_ATTR_RES_CM_IDN RDMA_NLDEV_ATTR_RES_CTXN RDMA_NLDEV_ATTR_LINK_TYPE RDMA_NLDEV_SYS_ATTR_NETNS_MODE RDMA_NLDEV_ATTR_DEV_PROTOCOL RDMA_NLDEV_NET_NS_FD RDMA_NLDEV_ATTR_CHARDEV_TYPE RDMA_NLDEV_ATTR_CHARDEV_NAME RDMA_NLDEV_ATTR_CHARDEV_ABI RDMA_NLDEV_ATTR_CHARDEV RDMA_NLDEV_ATTR_UVERBS_DRIVER_ID RDMA_NLDEV_ATTR_STAT_MODE RDMA_NLDEV_ATTR_STAT_RES RDMA_NLDEV_ATTR_STAT_AUTO_MODE_MASK RDMA_NLDEV_ATTR_STAT_COUNTER RDMA_NLDEV_ATTR_STAT_COUNTER_ENTRY RDMA_NLDEV_ATTR_STAT_COUNTER_ID RDMA_NLDEV_ATTR_STAT_HWCOUNTERS RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY_NAME RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY_VALUE RDMA_NLDEV_ATTR_DEV_DIM RDMA_NLDEV_ATTR_RES_RAW RDMA_NLDEV_ATTR_RES_CTX RDMA_NLDEV_ATTR_RES_CTX_ENTRY RDMA_NLDEV_ATTR_RES_SRQ RDMA_NLDEV_ATTR_RES_SRQ_ENTRY RDMA_NLDEV_ATTR_RES_SRQN RDMA_NLDEV_ATTR_MIN_RANGE RDMA_NLDEV_ATTR_MAX_RANGE RDMA_NLDEV_SYS_ATTR_COPY_ON_FORK RDMA_NLDEV_ATTR_MAX mlx5_sgmt_type MLX5_SGMT_TYPE_HW_CQPC MLX5_SGMT_TYPE_HW_SQPC MLX5_SGMT_TYPE_HW_RQPC MLX5_SGMT_TYPE_FULL_SRQC MLX5_SGMT_TYPE_FULL_CQC MLX5_SGMT_TYPE_FULL_EQC MLX5_SGMT_TYPE_FULL_QPC MLX5_SGMT_TYPE_SND_BUFF MLX5_SGMT_TYPE_RCV_BUFF MLX5_SGMT_TYPE_SRQ_BUFF MLX5_SGMT_TYPE_CQ_BUFF MLX5_SGMT_TYPE_EQ_BUFF MLX5_SGMT_TYPE_SX_SLICE MLX5_SGMT_TYPE_SX_SLICE_ALL MLX5_SGMT_TYPE_RDB MLX5_SGMT_TYPE_RX_SLICE_ALL MLX5_SGMT_TYPE_PRM_QUERY_QP MLX5_SGMT_TYPE_PRM_QUERY_CQ MLX5_SGMT_TYPE_PRM_QUERY_MKEY MLX5_SGMT_TYPE_MENU MLX5_SGMT_TYPE_TERMINATE MLX5_SGMT_TYPE_NUM mlx5_rsc_key rsc index1 index2 num_of_obj1 num_of_obj2 mlx5_rsc_dump_cmd mlx5_wqe_srq_next_seg next_wqe_index mlx5_wqe_data_seg MLX5_SRQ_FLAG_SIGNATURE mlx5_ib_create_srq mlx5_ib_create_srq_resp MLX5_SRQ_FLAG_ERR MLX5_SRQ_FLAG_WQ_SIG MLX5_SRQ_FLAG_RNDV mlx5_srq_attr db_record tm_log_list_size tm_next_tag tm_hw_phase_cnt tm_sw_phase_cnt MLX5_XRC_SRQC_STATE_GOOD MLX5_XRC_SRQC_STATE_ERROR mlx5_ifc_xrc_srqc_bits log_xrc_srq_size cont_srq reserved_at_22 reserved_at_46 user_index_equal_xrc_srqn reserved_at_81 db_record_addr_h db_record_addr_l reserved_at_17e MLX5_SRQC_STATE_GOOD MLX5_SRQC_STATE_ERROR mlx5_ifc_srqc_bits log_srq_size reserved_at_88 MLX5_RMPC_STATE_RDY MLX5_RMPC_STATE_ERR mlx5_ifc_rmpc_bits MLX5_XRQC_STATE_GOOD MLX5_XRQC_STATE_ERROR MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY MLX5_XRQC_TOPOLOGY_TAG_MATCHING MLX5_XRQC_OFFLOAD_RNDV mlx5_ifc_tag_matching_topology_context_bits log_matching_list_sz append_next_index sw_phase_cnt hw_phase_cnt mlx5_ifc_xrqc_bits rlkey tag_matching_topology_context mlx5_ifc_query_xrq_in_bits xrqn mlx5_ifc_query_xrc_srq_in_bits xrc_srqn mlx5_ifc_query_srq_in_bits mlx5_ifc_query_rmp_in_bits mlx5_ifc_rmp_bitmask_bits mlx5_ifc_modify_rmp_in_bits rmp_state mlx5_ifc_destroy_xrq_in_bits mlx5_ifc_destroy_xrc_srq_in_bits mlx5_ifc_destroy_srq_in_bits mlx5_ifc_destroy_rmp_in_bits mlx5_ifc_create_xrq_out_bits mlx5_ifc_create_xrq_in_bits xrq_context mlx5_ifc_create_xrc_srq_out_bits mlx5_ifc_create_xrc_srq_in_bits xrc_srq_context_entry xrc_srq_umem_valid mlx5_ifc_create_srq_out_bits mlx5_ifc_create_srq_in_bits srq_context_entry mlx5_ifc_create_rmp_out_bits mlx5_ifc_create_rmp_in_bits MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ mlx5_ifc_arm_xrc_srq_in_bits MLX5_ARM_RQ_IN_OP_MOD_SRQ MLX5_ARM_RQ_IN_OP_MOD_XRQ mlx5_ifc_arm_rq_in_bits srq_number ib_reg_wr MLX5_EXTENDED_UD_AV MLX5_PERM_LOCAL_READ MLX5_PERM_LOCAL_WRITE MLX5_PERM_REMOTE_READ MLX5_PERM_REMOTE_WRITE MLX5_PERM_ATOMIC MLX5_PERM_UMR_EN MLX5_MKEY_MASK_LEN MLX5_MKEY_MASK_PAGE_SIZE MLX5_MKEY_MASK_START_ADDR MLX5_MKEY_MASK_PD MLX5_MKEY_MASK_EN_RINVAL MLX5_MKEY_MASK_EN_SIGERR MLX5_MKEY_MASK_BSF_EN MLX5_MKEY_MASK_KEY MLX5_MKEY_MASK_QPN MLX5_MKEY_MASK_LR MLX5_MKEY_MASK_LW MLX5_MKEY_MASK_RR MLX5_MKEY_MASK_RW MLX5_MKEY_MASK_A MLX5_MKEY_MASK_SMALL_FENCE MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE MLX5_MKEY_MASK_FREE MLX5_MKEY_MASK_RELAXED_ORDERING_READ MLX5_UMR_TRANSLATION_OFFSET_EN MLX5_UMR_CHECK_NOT_FREE MLX5_UMR_CHECK_FREE MLX5_UMR_INLINE MLX5_MKEY_STATUS_FREE MLX5_MKEY_REMOTE_INVAL MLX5_MKEY_FLAG_SYNC_UMR MLX5_MKEY_BSF_EN mlx5_mkey_seg pcie_control qpn_mkey7_0 flags_pd bsfs_octo_size xlt_oct_size log2_page_size MLX5_FLAGS_INLINE MLX5_FLAGS_CHECK_FREE MLX5_ETH_WQE_L3_INNER_CSUM MLX5_ETH_WQE_L4_INNER_CSUM MLX5_ETH_WQE_L3_CSUM MLX5_ETH_WQE_L4_CSUM __empty_data inline_hdr mlx5_wqe_eth_seg swp_outer_l4_offset swp_outer_l3_offset swp_inner_l4_offset swp_inner_l3_offset cs_flags swp_flags flow_table_metadata mlx5_wqe_xrc_seg mlx5_wqe_datagram_seg mlx5_wqe_raddr_seg xlt_offset bsf_octowords mlx5_wqe_umr_ctrl_seg xlt_octowords mkey_mask xlt_offset_47_16 mlx5_seg_set_psv psv_num transient_sig mlx5_rwqe_sig mlx5_wqe_inline_seg mlx5_sig_type MLX5_DIF_CRC MLX5_DIF_IPCS mlx5_bsf_inl vld_refresh dif_apptag dif_reftag rp_inv_seed dif_inc_ref_guard_check dif_app_bitmask_check copy_byte_mask bs_selector rsvd_wflags rsvd_mflags mlx5_bsf_basic bsf_size_sbs check_byte_mask w_bfs_psv m_bfs_psv mlx5_bsf_ext t_init_gen_pro_size rsvd_epi_size w_tfs_psv m_tfs_psv mlx5_bsf w_inl m_inl mlx5_stride_block_entry mlx5_stride_block_ctrl_seg bcount_per_cycle repeat_count mlx5_wqe_eth_pad ib_uverbs_advise_mr_flag IB_UVERBS_ADVISE_MR_FLAG_FLUSH mlx5_ifc_odp_per_transport_service_cap_bits receive srq_receive mlx5_ifc_odp_cap_bits reserved_at_41 dc_odp_caps mlx5_ifc_page_fault_resume_in_bits page_fault_type wq_number MLX5_PFAULT_SUBTYPE_WQE MLX5_PFAULT_SUBTYPE_RDMA wqe_page_fault_type MLX5_WQE_PF_TYPE_RMP MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE MLX5_WQE_PF_TYPE_RESP MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC mlx5_eq_param irq_index mlx5_pagefault_type_flags MLX5_PFAULT_REQUESTOR MLX5_PFAULT_WRITE MLX5_PFAULT_RDMA mlx5_base_av mlx5_ib_devx_mr mlx5_pagefault event_subtype pf_frame io_virt bcnt MLX5_IB_NUM_PF_EQE MLX5_IB_NUM_PF_DRAIN prefetch_mr_work pf_flags mlx5_switchdev_event MLX5_SWITCHDEV_EVENT_PAIR MLX5_SWITCHDEV_EVENT_UNPAIR mlx5_eswitch_rep_ops unload get_proto_dev uverbs_obj_fd_type mlx5_ib_devx_methods MLX5_IB_METHOD_DEVX_OTHER MLX5_IB_METHOD_DEVX_QUERY_UAR MLX5_IB_METHOD_DEVX_QUERY_EQN MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT mlx5_ib_devx_other_attrs MLX5_IB_ATTR_DEVX_OTHER_CMD_IN MLX5_IB_ATTR_DEVX_OTHER_CMD_OUT mlx5_ib_devx_obj_create_attrs MLX5_IB_ATTR_DEVX_OBJ_CREATE_HANDLE MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_IN MLX5_IB_ATTR_DEVX_OBJ_CREATE_CMD_OUT mlx5_ib_devx_query_uar_attrs MLX5_IB_ATTR_DEVX_QUERY_UAR_USER_IDX MLX5_IB_ATTR_DEVX_QUERY_UAR_DEV_IDX mlx5_ib_devx_obj_destroy_attrs MLX5_IB_ATTR_DEVX_OBJ_DESTROY_HANDLE mlx5_ib_devx_obj_modify_attrs MLX5_IB_ATTR_DEVX_OBJ_MODIFY_HANDLE MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_IN MLX5_IB_ATTR_DEVX_OBJ_MODIFY_CMD_OUT mlx5_ib_devx_obj_query_attrs MLX5_IB_ATTR_DEVX_OBJ_QUERY_HANDLE MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_IN MLX5_IB_ATTR_DEVX_OBJ_QUERY_CMD_OUT mlx5_ib_devx_obj_query_async_attrs MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_HANDLE MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_CMD_IN MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_FD MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_WR_ID MLX5_IB_ATTR_DEVX_OBJ_QUERY_ASYNC_OUT_LEN mlx5_ib_devx_subscribe_event_attrs MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_HANDLE MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_OBJ_HANDLE MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_TYPE_NUM_LIST MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_FD_NUM MLX5_IB_ATTR_DEVX_SUBSCRIBE_EVENT_COOKIE mlx5_ib_devx_query_eqn_attrs MLX5_IB_ATTR_DEVX_QUERY_EQN_USER_VEC MLX5_IB_ATTR_DEVX_QUERY_EQN_DEV_EQN mlx5_ib_devx_obj_methods MLX5_IB_METHOD_DEVX_OBJ_CREATE MLX5_IB_METHOD_DEVX_OBJ_DESTROY MLX5_IB_METHOD_DEVX_OBJ_MODIFY MLX5_IB_METHOD_DEVX_OBJ_QUERY MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY mlx5_ib_devx_umem_reg_attrs MLX5_IB_ATTR_DEVX_UMEM_REG_HANDLE MLX5_IB_ATTR_DEVX_UMEM_REG_ADDR MLX5_IB_ATTR_DEVX_UMEM_REG_LEN MLX5_IB_ATTR_DEVX_UMEM_REG_ACCESS MLX5_IB_ATTR_DEVX_UMEM_REG_OUT_ID MLX5_IB_ATTR_DEVX_UMEM_REG_PGSZ_BITMAP mlx5_ib_devx_umem_dereg_attrs MLX5_IB_ATTR_DEVX_UMEM_DEREG_HANDLE mlx5_ib_devx_umem_methods MLX5_IB_METHOD_DEVX_UMEM_REG MLX5_IB_METHOD_DEVX_UMEM_DEREG mlx5_ib_devx_async_cmd_fd_alloc_attrs MLX5_IB_ATTR_DEVX_ASYNC_CMD_FD_ALLOC_HANDLE mlx5_ib_devx_async_event_fd_alloc_attrs MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_HANDLE MLX5_IB_ATTR_DEVX_ASYNC_EVENT_FD_ALLOC_FLAGS mlx5_ib_devx_async_cmd_fd_methods MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC mlx5_ib_devx_async_event_fd_methods MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC mlx5_ib_uapi_devx_async_cmd_hdr out_data mlx5_ib_uapi_devx_create_event_channel_flags MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA mlx5_ib_uapi_devx_async_event_hdr mlx5_ifc_ipv4_layout_bits mlx5_ifc_ipv6_layout_bits mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits ipv6_layout ipv4_layout MLX5_OBJ_TYPE_GENEVE_TLV_OPT MLX5_OBJ_TYPE_VIRTIO_NET_Q MLX5_OBJ_TYPE_MATCH_DEFINER MLX5_OBJ_TYPE_MKEY MLX5_OBJ_TYPE_QP MLX5_OBJ_TYPE_PSV MLX5_OBJ_TYPE_RMP MLX5_OBJ_TYPE_XRC_SRQ MLX5_OBJ_TYPE_RQ MLX5_OBJ_TYPE_SQ MLX5_OBJ_TYPE_TIR MLX5_OBJ_TYPE_TIS MLX5_OBJ_TYPE_DCT MLX5_OBJ_TYPE_XRQ MLX5_OBJ_TYPE_RQT MLX5_OBJ_TYPE_FLOW_COUNTER MLX5_OBJ_TYPE_CQ MLX5_CMD_OP_GENERAL_START MLX5_CMD_OP_GENERAL_END mlx5_ifc_fte_match_set_lyr_2_4_bits smac_47_16 smac_15_0 dmac_47_16 dmac_15_0 first_prio first_cfi first_vid ip_dscp ip_ecn cvlan_tag svlan_tag ip_version tcp_sport tcp_dport ipv4_ihl reserved_at_c4 ttl_hoplimit udp_dport src_ipv4_src_ipv6 dst_ipv4_dst_ipv6 mlx5_ifc_nvgre_key_bits mlx5_ifc_gre_key_bits nvgre mlx5_ifc_fte_match_set_misc_bits gre_c_present gre_k_present gre_s_present source_vhca_port source_sqn source_eswitch_owner_vhca_id outer_second_cvlan_tag inner_second_cvlan_tag outer_second_svlan_tag inner_second_svlan_tag reserved_at_64 gre_protocol vxlan_vni reserved_at_b8 geneve_vni geneve_oam outer_ipv6_flow_label inner_ipv6_flow_label geneve_opt_len geneve_protocol_type mlx5_ifc_fte_match_mpls_bits mpls_exp mpls_s_bos mlx5_ifc_fte_match_set_misc2_bits metadata_reg_a mlx5_ifc_fte_match_set_misc3_bits inner_tcp_seq_num outer_tcp_seq_num inner_tcp_ack_num outer_tcp_ack_num outer_vxlan_gpe_vni outer_vxlan_gpe_next_protocol outer_vxlan_gpe_flags icmp_header_data icmpv6_header_data icmp_type icmp_code icmpv6_type icmpv6_code gtpu_teid gtpu_msg_type gtpu_msg_flags gtpu_dw_2 gtpu_first_ext_dw_0 gtpu_dw_0 mlx5_ifc_fte_match_set_misc4_bits prog_sample_field_value_0 prog_sample_field_id_0 prog_sample_field_value_1 prog_sample_field_id_1 prog_sample_field_value_2 prog_sample_field_id_2 prog_sample_field_value_3 prog_sample_field_id_3 mlx5_ifc_fte_match_set_misc5_bits macsec_tag_0 macsec_tag_1 macsec_tag_2 macsec_tag_3 tunnel_header_0 tunnel_header_1 tunnel_header_2 tunnel_header_3 MLX5_UCTX_CAP_RAW_TX MLX5_UCTX_CAP_INTERNAL_DEV_RES mlx5_ifc_dest_format_struct_bits destination_eswitch_owner_vhca_id_valid packet_reformat destination_eswitch_owner_vhca_id mlx5_ifc_flow_counter_list_bits flow_counter_id mlx5_ifc_extended_dest_format_bits destination_entry packet_reformat_id mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits extended_dest_format flow_counter_list mlx5_ifc_fte_match_param_bits outer_headers misc_parameters inner_headers misc_parameters_2 misc_parameters_3 misc_parameters_4 misc_parameters_5 mlx5_ifc_mac_address_layout_bits mac_addr_47_32 mac_addr_31_0 mlx5_ifc_vlan_bits ethtype cfi mlx5_ifc_exe_aso_ctrl_flow_meter_bits return_reg_id aso_type init_color meter_id mlx5_ifc_exe_aso_ctrl exe_aso_ctrl_flow_meter mlx5_ifc_execute_aso_bits aso_object_id exe_aso_ctrl mlx5_ifc_flow_context_bits extended_destination flow_source reserved_at_84 destination_list_size flow_counter_list_size modify_header_id ipsec_obj_id reserved_at_1300 mlx5_ifc_scheduling_context_bits element_type element_attributes parent_element_id bw_share max_average_bw mlx5_ifc_set_l2_table_entry_in_bits vlan_valid mlx5_ifc_set_fte_in_bits other_vport vport_number table_type modify_enable_mask flow_index flow_context mlx5_ifc_query_tis_in_bits mlx5_ifc_query_tir_in_bits mlx5_ifc_query_sq_in_bits mlx5_ifc_query_scheduling_element_in_bits scheduling_hierarchy scheduling_element_id mlx5_ifc_query_rqt_in_bits mlx5_ifc_query_rq_in_bits mlx5_ifc_query_mkey_in_bits reserved_at_61 mlx5_ifc_query_l2_table_entry_in_bits mlx5_ifc_flow_table_context_bits reformat_en decap_en table_miss_action table_miss_id lag_master_next_table_id sw_owner_icm_root_1 sw_owner_icm_root_0 mlx5_ifc_query_flow_table_in_bits mlx5_ifc_query_fte_in_bits mlx5_ifc_general_obj_in_cmd_hdr_bits vhca_tunnel_id log_obj_range mlx5_ifc_general_obj_out_cmd_hdr_bits mlx5_ifc_query_flow_group_in_bits mlx5_ifc_query_flow_counter_in_bits num_of_counters mlx5_ifc_query_packet_reformat_context_in_bits mlx5_ifc_alloc_packet_reformat_context_out_bits mlx5_ifc_dealloc_packet_reformat_context_in_bits reserved_20 reserved_60 mlx5_ifc_alloc_modify_header_context_out_bits mlx5_ifc_dealloc_modify_header_context_in_bits mlx5_ifc_query_modify_header_context_in_bits mlx5_ifc_query_cq_in_bits mlx5_ifc_modify_tir_bitmask_bits self_lb_en reserved_at_3c reserved_at_3e packet_merge mlx5_ifc_modify_tir_in_bits mlx5_ifc_modify_scheduling_element_in_bits scheduling_context mlx5_ifc_rqt_bitmask_bits rqn_list mlx5_ifc_modify_rqt_in_bits mlx5_ifc_destroy_scheduling_element_in_bits mlx5_ifc_destroy_psv_in_bits psvn mlx5_ifc_destroy_mkey_in_bits mlx5_ifc_destroy_flow_table_in_bits mlx5_ifc_destroy_flow_group_in_bits mlx5_ifc_destroy_cq_in_bits mlx5_ifc_delete_vxlan_udp_dport_in_bits vxlan_udp_port mlx5_ifc_delete_l2_table_entry_in_bits mlx5_ifc_delete_fte_in_bits mlx5_ifc_dealloc_flow_counter_in_bits mlx5_ifc_create_tis_out_bits mlx5_ifc_create_scheduling_element_out_bits mlx5_ifc_create_scheduling_element_in_bits mlx5_ifc_create_rqt_out_bits mlx5_ifc_create_rq_out_bits mlx5_ifc_create_psv_out_bits psv0_index psv1_index psv2_index psv3_index mlx5_ifc_create_psv_in_bits num_psv mlx5_ifc_create_flow_table_out_bits mlx5_ifc_create_flow_table_in_bits flow_table_context mlx5_ifc_create_flow_group_out_bits mlx5_ifc_create_flow_group_in_bits source_eswitch_owner_vhca_id_valid start_flow_index end_flow_index match_definer_id match_criteria_enable match_criteria reserved_at_1200 mlx5_ifc_create_cq_out_bits mlx5_ifc_arm_xrq_in_bits mlx5_ifc_alloc_flow_counter_out_bits mlx5_ifc_alloc_flow_counter_in_bits flow_counter_bulk_log_size flow_counter_bulk mlx5_ifc_add_vxlan_udp_dport_in_bits mlx5_ifc_mtt_bits ptag_63_32 ptag_31_8 wr_en rd_en mlx5_ifc_modify_flow_table_in_bits mlx5_ifc_umem_bits num_of_mtt mtt mlx5_ifc_uctx_bits mlx5_ifc_create_umem_in_bits mlx5_ifc_create_umem_out_bits umem_id mlx5_ifc_destroy_umem_in_bits mlx5_ifc_create_uctx_in_bits mlx5_ifc_create_uctx_out_bits mlx5_ifc_destroy_uctx_in_bits mlx5_ifc_affiliated_event_header_bits devx_mr core_dct core_cq flow_counter_bulk_size devx_obj dinlen dinbox event_sub devx_obj_flags DEVX_OBJ_FLAGS_INDIRECT_MKEY DEVX_OBJ_FLAGS_DCT DEVX_OBJ_FLAGS_CQ devx_async_data ev_file cmd_out_len devx_async_cmd_event_file uobj ev_queue devx_async_event_data devx_event object_ids unaffiliated_list devx_obj_event obj_sub_list devx_event_subscription file_list xa_list is_cleaned xa_key_level1 xa_key_level2 devx_async_event_file subscribed_events_list omit_data is_overflow_err is_destroyed devx_umem devx_umem_reg_cmd devx_async_event_queue bytes_in_use ib_uverbs_flow_action_esp_keymat_aes_gcm_iv_algo IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ ib_uverbs_flow_action_esp_flags IB_UVERBS_FLOW_ACTION_ESP_FLAGS_INLINE_CRYPTO IB_UVERBS_FLOW_ACTION_ESP_FLAGS_FULL_OFFLOAD IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TUNNEL IB_UVERBS_FLOW_ACTION_ESP_FLAGS_TRANSPORT IB_UVERBS_FLOW_ACTION_ESP_FLAGS_DECRYPT IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW ib_flow_flags IB_FLOW_ATTR_FLAGS_DONT_TRAP IB_FLOW_ATTR_FLAGS_EGRESS IB_FLOW_ATTR_FLAGS_RESERVED ib_flow_action_attrs_esp_flags IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS ib_uflow_resources collection_num collection ib_uflow_object mlx5_ib_flow_matcher_create_attrs MLX5_IB_ATTR_FLOW_MATCHER_CREATE_HANDLE MLX5_IB_ATTR_FLOW_MATCHER_MATCH_MASK MLX5_IB_ATTR_FLOW_MATCHER_FLOW_TYPE MLX5_IB_ATTR_FLOW_MATCHER_MATCH_CRITERIA MLX5_IB_ATTR_FLOW_MATCHER_FLOW_FLAGS MLX5_IB_ATTR_FLOW_MATCHER_FT_TYPE mlx5_ib_flow_matcher_destroy_attrs MLX5_IB_ATTR_FLOW_MATCHER_DESTROY_HANDLE mlx5_ib_flow_matcher_methods MLX5_IB_METHOD_FLOW_MATCHER_CREATE MLX5_IB_METHOD_FLOW_MATCHER_DESTROY mlx5_ib_match_params match_params mlx5_ib_flow_type MLX5_IB_FLOW_TYPE_NORMAL MLX5_IB_FLOW_TYPE_SNIFFER MLX5_IB_FLOW_TYPE_ALL_DEFAULT MLX5_IB_FLOW_TYPE_MC_DEFAULT mlx5_ib_create_flow_flags MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DEFAULT_MISS MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DROP mlx5_ib_create_flow_attrs MLX5_IB_ATTR_CREATE_FLOW_HANDLE MLX5_IB_ATTR_CREATE_FLOW_MATCH_VALUE MLX5_IB_ATTR_CREATE_FLOW_DEST_QP MLX5_IB_ATTR_CREATE_FLOW_DEST_DEVX MLX5_IB_ATTR_CREATE_FLOW_MATCHER MLX5_IB_ATTR_CREATE_FLOW_ARR_FLOW_ACTIONS MLX5_IB_ATTR_CREATE_FLOW_TAG MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX MLX5_IB_ATTR_CREATE_FLOW_ARR_COUNTERS_DEVX_OFFSET MLX5_IB_ATTR_CREATE_FLOW_FLAGS mlx5_ib_flow_methods MLX5_IB_METHOD_CREATE_FLOW MLX5_IB_METHOD_DESTROY_FLOW mlx5_ib_flow_action_methods MLX5_IB_METHOD_FLOW_ACTION_CREATE_MODIFY_HEADER MLX5_IB_METHOD_FLOW_ACTION_CREATE_PACKET_REFORMAT mlx5_ib_create_flow_action_create_modify_header_attrs MLX5_IB_ATTR_CREATE_MODIFY_HEADER_HANDLE MLX5_IB_ATTR_CREATE_MODIFY_HEADER_ACTIONS_PRM MLX5_IB_ATTR_CREATE_MODIFY_HEADER_FT_TYPE mlx5_ib_create_flow_action_create_packet_reformat_attrs MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_HANDLE MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_TYPE MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_FT_TYPE MLX5_IB_ATTR_CREATE_PACKET_REFORMAT_DATA_BUF mlx5_ib_uapi_flow_action_flags MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA mlx5_ib_uapi_flow_table_type MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_TX mlx5_ib_uapi_flow_action_packet_reformat_type MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 MLX5_IB_UAPI_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL mlx5_ifc_flow_table_eswitch_cap_bits fdb_to_vport_reg_c_id fdb_modify_header_fwd_to_table fdb_ipv4_ttl_modify multi_fdb_encap egress_acl_forward_to_vport fdb_multi_path_to_table reserved_at_1d flow_table_properties_nic_esw_fdb flow_table_properties_esw_acl_ingress flow_table_properties_esw_acl_egress sw_steering_fdb_action_drop_icm_address_rx sw_steering_fdb_action_drop_icm_address_tx sw_steering_uplink_icm_address_rx sw_steering_uplink_icm_address_tx reserved_at_1900 mlx5_flow_destination_type MLX5_FLOW_DESTINATION_TYPE_VPORT MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE MLX5_FLOW_DESTINATION_TYPE_TIR MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER MLX5_FLOW_DESTINATION_TYPE_UPLINK MLX5_FLOW_DESTINATION_TYPE_PORT MLX5_FLOW_DESTINATION_TYPE_COUNTER MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM MLX5_FLOW_CONTEXT_ACTION_ALLOW MLX5_FLOW_CONTEXT_ACTION_DROP MLX5_FLOW_CONTEXT_ACTION_FWD_DEST MLX5_FLOW_CONTEXT_ACTION_COUNT MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT MLX5_FLOW_CONTEXT_ACTION_DECAP MLX5_FLOW_CONTEXT_ACTION_MOD_HDR MLX5_FLOW_CONTEXT_ACTION_VLAN_POP MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO mlx5_reformat_ctx_type MLX5_REFORMAT_TYPE_L2_TO_VXLAN MLX5_REFORMAT_TYPE_L2_TO_NVGRE MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL MLX5_REFORMAT_TYPE_INSERT_HDR MLX5_REFORMAT_TYPE_REMOVE_HDR mlx5_mpls_supported_fields MLX5_FIELD_SUPPORT_MPLS_LABEL MLX5_FIELD_SUPPORT_MPLS_EXP MLX5_FIELD_SUPPORT_MPLS_S_BOS MLX5_FIELD_SUPPORT_MPLS_TTL MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO MLX5_FLOW_CONTEXT_ACTION_ENCRYPT MLX5_FLOW_CONTEXT_ACTION_DECRYPT MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_NS MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT MLX5_FLOW_TABLE_TUNNEL_EN_DECAP MLX5_FLOW_TABLE_TERMINATION MLX5_FLOW_TABLE_UNMANAGED MLX5_FLOW_TABLE_OTHER_VPORT FDB_BYPASS_PATH FDB_TC_OFFLOAD FDB_FT_OFFLOAD FDB_TC_MISS FDB_BR_OFFLOAD FDB_SLOW_PATH FDB_PER_VPORT FLOW_CONTEXT_HAS_TAG mlx5_flow_context mlx5_flow_spec pkt_reformat mlx5_pkt_reformat tir_num ft_num counter_id sampler_id mlx5_flow_destination max_num_groups num_reserved_entries mlx5_flow_table_attr max_fte next_ft mlx5_fs_vlan esp_id mlx5_flow_act modify_hdr mlx5_modify_hdr mlx5_pkt_reformat_params param_0 param_1 mlx5_accel_esp_aes_gcm_keymat_iv_algo MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ mlx5_accel_esp_flags MLX5_ACCEL_ESP_FLAGS_TUNNEL MLX5_ACCEL_ESP_FLAGS_TRANSPORT MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP mlx5_accel_esp_action MLX5_ACCEL_ESP_ACTION_DECRYPT MLX5_ACCEL_ESP_ACTION_ENCRYPT mlx5_accel_esp_keymats MLX5_ACCEL_ESP_KEYMAT_AES_NONE MLX5_ACCEL_ESP_KEYMAT_AES_GCM mlx5_accel_esp_replay MLX5_ACCEL_ESP_REPLAY_NONE MLX5_ACCEL_ESP_REPLAY_BMP aes_gcm_keymat seq_iv mlx5_accel_esp_xfrm_attrs sa_handle replay_type keymat_type mlx5_accel_esp_xfrm MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA MLX5_IB_FLOW_ACTION_MODIFY_HEADER MLX5_IB_FLOW_ACTION_PACKET_REFORMAT MLX5_IB_FLOW_ACTION_DECAP mlx5_ib_flow_handler ibflow ibcounters flow_matcher mlx5_ib_flow_matcher matcher_mask mask_len ib_flags esp_aes_gcm flow_action_raw mlx5_ib_flow_action ib_action MATCH_CRITERIA_ENABLE_OUTER_BIT MATCH_CRITERIA_ENABLE_MISC_BIT MATCH_CRITERIA_ENABLE_INNER_BIT MATCH_CRITERIA_ENABLE_MISC2_BIT valid_spec VALID_SPEC_INVALID VALID_SPEC_VALID VALID_SPEC_NA flow_table_type MLX5_IB_FT_RX MLX5_IB_FT_TX LEFTOVERS_MC LEFTOVERS_UC flow_attr eth_flow mlx5_ib_pp_obj_methods MLX5_IB_METHOD_PP_OBJ_ALLOC MLX5_IB_METHOD_PP_OBJ_DESTROY mlx5_ib_pp_alloc_attrs MLX5_IB_ATTR_PP_OBJ_ALLOC_HANDLE MLX5_IB_ATTR_PP_OBJ_ALLOC_CTX MLX5_IB_ATTR_PP_OBJ_ALLOC_FLAGS MLX5_IB_ATTR_PP_OBJ_ALLOC_INDEX mlx5_ib_pp_obj_destroy_attrs MLX5_IB_ATTR_PP_OBJ_DESTROY_HANDLE mlx5_ib_uapi_pp_alloc_flags MLX5_IB_UAPI_PP_ALLOC_FLAGS_DEDICATED_INDEX mlx5_ib_pp mlx5_ib_query_pd_attrs MLX5_IB_ATTR_QUERY_PD_HANDLE MLX5_IB_ATTR_QUERY_PD_RESP_PDN mlx5_ib_pd_methods MLX5_IB_METHOD_PD_QUERY mlx5_ib_device_methods MLX5_IB_METHOD_QUERY_PORT mlx5_ib_query_port_attrs MLX5_IB_ATTR_QUERY_PORT_PORT_NUM MLX5_IB_ATTR_QUERY_PORT mlx5_ib_uapi_query_port_flags MLX5_IB_UAPI_QUERY_PORT_VPORT MLX5_IB_UAPI_QUERY_PORT_VPORT_VHCA_ID MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_RX MLX5_IB_UAPI_QUERY_PORT_VPORT_STEERING_ICM_TX MLX5_IB_UAPI_QUERY_PORT_VPORT_REG_C0 MLX5_IB_UAPI_QUERY_PORT_ESW_OWNER_VHCA_ID mlx5_ib_uapi_reg mlx5_ib_uapi_query_port vport_vhca_id esw_owner_vhca_id vport_steering_icm_rx vport_steering_icm_tx reg_c0 mlx5_ifc_fpga_shell_caps_bits max_num_qps total_rcv_credits log_ddr_size max_fpga_qp_msg_size mlx5_ifc_fpga_cap_bits fpga_id fpga_device register_file_ver fpga_ctrl_modify access_reg_query_mode access_reg_modify_mode image_version image_date image_time shell_version shell_caps reserved_at_380 ieee_vendor_id sandbox_product_version sandbox_product_id sandbox_basic_caps sandbox_extended_caps_len sandbox_extended_caps_addr fpga_ddr_start_addr fpga_cr_space_start_addr fpga_ddr_size fpga_cr_space_size MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE MLX5_SET_HCA_CAP_OP_MOD_ODP MLX5_SET_HCA_CAP_OP_MOD_ATOMIC MLX5_SET_HCA_CAP_OP_MOD_ROCE mlx5_ifc_e_switch_cap_bits vport_svlan_strip vport_cvlan_strip vport_svlan_insert vport_cvlan_insert_if_not_exist vport_cvlan_insert_overwrite vport_cvlan_insert_always esw_shared_ingress_acl esw_uplink_ingress_acl root_ft_on_other_esw reserved_at_a esw_functions_changed ecpf_vport_exists counter_eswitch_affinity merged_eswitch nic_vport_node_guid_modify nic_vport_port_guid_modify vxlan_encap_decap nvgre_encap_decap log_max_fdb_encap_uplink reserved_2b log_max_esw_sf esw_sf_base_id mlx5_ifc_debug_cap_bits core_dump_general core_dump_qp resource_dump stall_detect reserved_at_23 mlx5_ifc_calc_op op_swap_endianness op_min op_xor op_or op_and op_max op_add mlx5_ifc_vector_calc_cap_bits calc_matrix max_vec_count max_chunk_size calc0 calc1 calc2 calc3 mlx5_ifc_tls_cap_bits tls_1_2_aes_gcm_128 tls_1_3_aes_gcm_128 tls_1_2_aes_gcm_256 tls_1_3_aes_gcm_256 mlx5_ifc_cmd_hca_cap_2_bits max_reformat_insert_size max_reformat_insert_offset max_reformat_remove_size max_reformat_remove_offset mlx5_ifc_hca_cap_union_bits cmd_hca_cap cmd_hca_cap_2 odp_cap atomic_caps roce_cap per_protocol_networking_offload_caps flow_table_nic_cap flow_table_eswitch_cap e_switch_cap vector_calc_cap qos_cap debug_cap fpga_cap tls_cap device_mem_cap virtio_emulation_cap mlx5_ifc_query_hca_cap_out_bits mlx5_ifc_query_hca_cap_in_bits other_function mlx5_ifc_query_esw_vport_context_in_bits mlx5_cap_mode HCA_CAP_OPMOD_GET_MAX HCA_CAP_OPMOD_GET_CUR nreq send_signaled __begin_wqe __cache_work_func __mlx5_ib_add max_num_sg max_num_meta_sg __mlx5_ib_alloc_mr rsn __mlx5_ib_cq_clean attr_mask __mlx5_ib_modify_qp __mlx5_ib_qp_set_counter __mlx5_ib_qp_set_raw_qp_counter __mlx5_ib_remove pgsz_bitmap page_offset_bits pgoff_bitmask page_offset_quantized __mlx5_umem_find_best_quantized_pgoff __set_srq_page_size ft_prio _create_flow_rule init_attr _create_kernel_qp fs_matcher flow_act dst_num _create_raw_flow_rule _create_user_qp mcast _get_flow_table _mlx5_alloc_mkey_descs _mlx5_core_destroy_dct attrs_bundle _uverbs_copy_from add_keys mkc alloc_cache_mr alloc_cacheable_mr alloc_var_entry begin_wqe dyn_bfreg bfregn_to_uar_index board_id_show cache_work_func calc_sq_size check_valid_flow copy_resize_cqes create_cache_mr cqb create_cq_user create_dci create_dct create_flow_rule_vport_sq create_gsi_ud_qp create_ib_ah create_mkey_callback create_raw_packet_qp qp_flags_en create_raw_packet_qp_tir create_real_mr rsc_type create_resource_common create_rmp_cmd rwq create_rq create_rss_raw_qp_tir create_srq_cmd create_srq_kernel create_srq_user create_user_qp create_user_rq create_xrc_srq_cmd create_xrc_tgt_qp create_xrq_cmd deallocate_uars delay_drop_handler delay_drop_timeout_read delay_drop_timeout_write delay_time_func delayed_cache_work_func deliver_event destroy_qp_common devx_async_cmd_event_destroy_uobj devx_async_cmd_event_poll devx_async_cmd_event_read devx_async_event_destroy_uobj devx_async_event_poll devx_async_event_read devx_cleanup_subscription eqe devx_cq_comp devx_event_notifier devx_free_subscription devx_get_created_obj_id devx_get_obj_id devx_get_uid devx_is_obj_query_cmd devx_is_supported devx_is_valid_obj_id din devx_obj_build_destroy_cmd devx_obj_cleanup devx_query_callback devx_set_umem_valid devx_umem_cleanup devx_umem_reg_cmd_alloc fill_res_raw fill_vport_icm_addr mlx5_opcode finish_wqe ib_attr flow_is_multicast_only flow_matcher_cleanup free_implicit_child_mr_work fw_pages_show generate_completions ib_send_cq ib_recv_cq get_cqs dest_type get_dests ft_type get_flow_table get_octo_len get_param get_port_state get_prefetchable_mr get_qp_ts_format srqc get_srqc get_sw_cqe get_tx_affinity get_tx_affinity_rr get_wq handle_alloc_dm_memic handle_alloc_dm_sw_icm sdrain handle_drain_completion psv_index handle_psv handle_reg_mr_integrity handle_responder handle_single_completion hca_type_show hw_rev_show implicit_get_child_mr internal_fill_odp_caps limit_read limit_write mbox_alloc ignore_mkey ignore_bkey in_wc in_grh in_mad response_mad mlx5_MAD_IFC mlx5_alloc_integrity_descs mlx5_cleanup_qp_table mlx5_cleanup_srq_table mlx5_cmd_alloc_memic mlx5_cmd_alloc_transport_domain is_srq mlx5_cmd_arm_srq mlx5_cmd_attach_mcg mlx5_cmd_create_srq mlx5_cmd_dealloc_memic mlx5_cmd_dealloc_memic_op mlx5_cmd_dealloc_pd mlx5_cmd_dealloc_transport_domain mlx5_cmd_destroy_rqt mlx5_cmd_destroy_srq mlx5_cmd_destroy_tir mlx5_cmd_destroy_tis mlx5_cmd_detach_mcg mlx5_cmd_dump_fill_mkey mlx5_cmd_get_srq inb outb opmod mlx5_cmd_mad_ifc mlx5_cmd_null_mkey cong_point mlx5_cmd_query_cong_params mlx5_cmd_query_srq mlx5_cmd_xrcd_alloc mlx5_cmd_xrcd_dealloc mlx5_core_create_dct mlx5_core_create_rq_tracked mlx5_core_create_sq_tracked mlx5_core_dct_query mlx5_core_destroy_dct mlx5_core_destroy_qp mlx5_core_destroy_rq_tracked mlx5_core_destroy_sq_tracked mlx5_core_put_rsc mlx5_core_qp_modify mlx5_core_qp_query res_num mlx5_core_res_hold mlx5_core_res_put timeout_usec mlx5_core_set_delay_drop mlx5_core_xrcd_alloc mlx5_core_xrcd_dealloc inl mlx5_fill_inl_bsf mlx5_free_priv_descs mlx5_get_cc_param_val mlx5_get_roce_udp_sport_min mlx5_get_rsc mlx5_get_vport_access_method mlx5_ib_add_gid mlx5_ib_add_outstanding_wr mlx5_ib_advise_mr mlx5_ib_advise_mr_prefetch mlx5_ib_alloc_counters mlx5_ib_alloc_dm mlx5_ib_alloc_hw_device_stats mlx5_ib_alloc_hw_port_stats mlx5_ib_alloc_implicit_mr mlx5_ib_alloc_mr mlx5_ib_alloc_mr_integrity mlx5_ib_alloc_pd mlx5_ib_alloc_pi_mr mlx5_ib_alloc_ucontext mlx5_ib_alloc_xrcd mlx5_ib_arm_cq mlx5_ib_bind_slave_port mr_status mlx5_ib_check_mr_status mlx5_ib_cleanup mlx5_ib_cleanup_cong_debugfs mlx5_ib_cleanup_multiport_master mlx5_ib_counter_alloc_stats mlx5_ib_counter_bind_qp mlx5_ib_counter_dealloc mlx5_ib_counter_unbind_qp mlx5_ib_counter_update_stats mlx5_ib_counters_cleanup mlx5_ib_counters_clear_description mlx5_ib_counters_init mlx5_ib_cq_clean mlx5_ib_cq_comp mlx5_ib_cq_event mlx5_ib_create_ah mlx5_ib_create_counters mlx5_ib_create_flow_action_esp mlx5_ib_create_gsi mlx5_ib_create_mkey mlx5_ib_create_rwq_ind_table mlx5_ib_create_xlt_wr mlx5_ib_db_map_user mlx5_ib_db_unmap_user qp_attr qp_attr_mask qp_init_attr mlx5_ib_dct_query_qp mlx5_ib_dealloc_counters mlx5_ib_dealloc_dm mw mlx5_ib_dealloc_mw mlx5_ib_dealloc_pd mlx5_ib_dealloc_transport_domain ibcontext mlx5_ib_dealloc_ucontext mlx5_ib_dealloc_xrcd mlx5_ib_del_gid mlx5_ib_dereg_mr mlx5_ib_destroy_ah mlx5_ib_destroy_counters mlx5_ib_destroy_cq mlx5_ib_destroy_dct mlx5_ib_destroy_flow mlx5_ib_destroy_flow_action mlx5_ib_destroy_gsi mlx5_ib_destroy_qp mlx5_ib_destroy_rwq_ind_table mlx5_ib_destroy_srq mlx5_ib_destroy_wq mlx5_ib_dev_res_cleanup mlx5_ib_dev_res_init mlx5_ib_devx_cleanup is_user mlx5_ib_devx_create mlx5_ib_devx_destroy mlx5_ib_devx_init mlx5_ib_disable_lb mlx5_ib_disassociate_ucontext mlx5_ib_dm_mmap_free mlx5_ib_dmabuf_invalidate_cb mlx5_ib_drain_qp_done mlx5_ib_drain_rq mlx5_ib_drain_sq mlx5_ib_enable_driver mlx5_ib_enable_lb mlx5_ib_eq_pf_action mlx5_ib_eq_pf_int mlx5_ib_eq_pf_process mlx5_ib_eqe_pf_action mlx5_ib_event mlx5_ib_event_slave_port mlx5_ib_fill_counters mlx5_ib_flow_counters_set_data mlx5_ib_free_bfreg mlx5_ib_free_odp_mr mlx5_ib_free_srq_wqe mlx5_ib_free_xlt mlx5_ib_fs_cleanup mlx5_ib_fs_init mlx5_ib_generate_wc mlx5_ib_get_counters_id mlx5_ib_get_cqe_size acc mlx5_ib_get_dma_mr mlx5_ib_get_hw_stats mlx5_ib_get_ibdev_from_mpi ib_port_num mlx5_ib_get_native_port_mdev mlx5_ib_get_netdev mlx5_ib_get_rep_netdev mlx5_ib_get_vf_config mlx5_ib_get_vf_guid mlx5_ib_get_vf_stats mlx5_ib_gsi_modify_qp mlx5_ib_gsi_pkey_change bad_wr mlx5_ib_gsi_post_recv mlx5_ib_gsi_post_send mlx5_ib_gsi_query_qp mlx5_ib_gsi_silent_drop mlx5_ib_handle_event mlx5_ib_handle_internal_error mlx5_ib_handler_MLX5_IB_METHOD_CREATE_FLOW mlx5_ib_handler_MLX5_IB_METHOD_DEVX_ASYNC_CMD_FD_ALLOC mlx5_ib_handler_MLX5_IB_METHOD_DEVX_ASYNC_EVENT_FD_ALLOC mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OBJ_ASYNC_QUERY mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OBJ_CREATE mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OBJ_MODIFY mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OBJ_QUERY mlx5_ib_handler_MLX5_IB_METHOD_DEVX_OTHER mlx5_ib_handler_MLX5_IB_METHOD_DEVX_QUERY_EQN mlx5_ib_handler_MLX5_IB_METHOD_DEVX_QUERY_UAR mlx5_ib_handler_MLX5_IB_METHOD_DEVX_SUBSCRIBE_EVENT mlx5_ib_handler_MLX5_IB_METHOD_DEVX_UMEM_REG mlx5_ib_handler_MLX5_IB_METHOD_DM_MAP_OP_ADDR mlx5_ib_handler_MLX5_IB_METHOD_DM_QUERY mlx5_ib_handler_MLX5_IB_METHOD_FLOW_ACTION_CREATE_MODIFY_HEADER mlx5_ib_handler_MLX5_IB_METHOD_FLOW_ACTION_CREATE_PACKET_REFORMAT mlx5_ib_handler_MLX5_IB_METHOD_FLOW_MATCHER_CREATE mlx5_ib_handler_MLX5_IB_METHOD_PD_QUERY mlx5_ib_handler_MLX5_IB_METHOD_PP_OBJ_ALLOC mlx5_ib_handler_MLX5_IB_METHOD_QUERY_PORT mlx5_ib_handler_MLX5_IB_METHOD_UAR_OBJ_ALLOC mlx5_ib_handler_MLX5_IB_METHOD_VAR_OBJ_ALLOC mlx5_ib_init mlx5_ib_init_cong_debugfs mlx5_ib_init_dmabuf_mr mlx5_ib_init_multiport_master mlx5_ib_init_odp_mr mni mlx5_ib_invalidate_range mlx5_ib_lock_cqs sg_offset mlx5_ib_map_mr_sg data_sg data_sg_nents data_sg_offset meta_sg meta_sg_nents meta_sg_offset mlx5_ib_map_mr_sg_pi mlx5_ib_mcg_attach mlx5_ib_mcg_detach mlx5_ib_mmap mlx5_ib_mmap_free cq_count mlx5_ib_modify_cq mlx5_ib_modify_dct mlx5_ib_modify_device mlx5_ib_modify_flow_action_esp mlx5_ib_modify_port mlx5_ib_modify_srq wq_attr wq_attr_mask pfault mlx5_ib_mr_rdma_pfault_handler mlx5_ib_mr_wqe_pfault_handler mlx5_ib_odp_cleanup_one mlx5_ib_odp_init mlx5_ib_odp_init_one mlx5_ib_page_fault_resume mlx5_ib_poll_cq mlx5_ib_populate_pas mlx5_ib_port_link_layer mlx5_ib_post_recv mlx5_ib_post_recv_nodrain mlx5_ib_post_send mlx5_ib_post_send_nodrain umrwr mlx5_ib_post_send_wait mlx5_ib_post_srq_recv mlx5_ib_prefetch_mr_work mad_flags out_mad_size out_mad_pkey_index mlx5_ib_process_mad mlx5_ib_put_native_port_mdev mlx5_ib_qp_event mlx5_ib_qp_set_counter mlx5_ib_query_ah uhw mlx5_ib_query_device mlx5_ib_query_ext_ppcnt_counters mlx5_ib_query_gid mlx5_ib_query_pkey mlx5_ib_query_port mlx5_ib_query_q_counters mlx5_ib_query_qp srq_attr mlx5_ib_query_srq mlx5_ib_query_ucontext read_attr mlx5_ib_read_counters wq_offset wq_wqe_cnt wq_wqe_shift bytes_copied mlx5_ib_read_user_wqe_common mlx5_ib_read_wqe_rq mlx5_ib_read_wqe_sq mlx5_ib_read_wqe_srq mlx5_ib_reg_dm_mr mlx5_ib_reg_user_mr mlx5_ib_reg_user_mr_dmabuf mlx5_ib_rep_query_pkey mlx5_ib_rep_query_port mlx5_ib_rep_to_dev new_access_flags new_pd mlx5_ib_rereg_user_mr mlx5_ib_restrack_init mlx5_ib_rn_get_params mlx5_ib_roce_cleanup mlx5_ib_roce_init mlx5_ib_set_cc_param_mask_val mlx5_ib_set_vf_guid mlx5_ib_set_vf_link_state sg_offset_p meta_sgl meta_sg_offset_p mlx5_ib_sg_to_klms mlx5_ib_srq_event mlx5_ib_stage_bfrag_cleanup mlx5_ib_stage_bfrag_init mlx5_ib_stage_caps_cleanup mlx5_ib_stage_caps_init mlx5_ib_stage_cong_debugfs_cleanup mlx5_ib_stage_cong_debugfs_init mlx5_ib_stage_delay_drop_cleanup mlx5_ib_stage_delay_drop_init mlx5_ib_stage_dev_notifier_cleanup mlx5_ib_stage_dev_notifier_init mlx5_ib_stage_ib_reg_cleanup mlx5_ib_stage_ib_reg_init mlx5_ib_stage_init_cleanup mlx5_ib_stage_init_init mlx5_ib_stage_non_default_cb mlx5_ib_stage_post_ib_reg_umr_init mlx5_ib_stage_pre_ib_reg_umr_cleanup mlx5_ib_stage_raw_eth_non_default_cb mlx5_ib_stage_uar_cleanup mlx5_ib_stage_uar_init mlx5_ib_test_wc mlx5_ib_umr_done mlx5_ib_unbind_slave_port mlx5_ib_unlock_cqs mlx5_ib_update_mr_pas mlx5_ib_update_xlt mlx5_ib_vport_rep_load mlx5_ib_vport_rep_unload mlx5_ib_wq_event mlx5_init_qp_table mlx5_init_srq_table mlx5_invalidate_umem mlx5_mr_cache_alloc mlx5_mr_cache_cleanup mlx5_mr_cache_init mlx5_netdev_event mlx5_odp_init_mr_cache_entry mlx5_odp_populate_xlt cur_qp mlx5_poll_one mlx5_port_immutable mlx5_port_rep_immutable mlx5_qpc_create_qp mlx5_query_ext_port_caps mlx5_query_hca_port mlx5_query_mad_ifc_gids mlx5_query_mad_ifc_max_pkeys mlx5_query_mad_ifc_node_desc mlx5_query_mad_ifc_node_guid mlx5_query_mad_ifc_pkey mlx5_query_mad_ifc_port out_mad mlx5_query_mad_ifc_smp_attr_node_info mlx5_query_mad_ifc_system_image_guid mlx5_query_mad_ifc_vendor_id mlx5_query_port_roce mlx5_set_page mlx5_set_page_pi mlx5_set_path mlx5r_mp_probe mlx5r_mp_remove mlx5r_odp_create_eq mlx5r_probe mlx5r_remove mlx5r_rep_cleanup mlx5r_rep_init mlx5r_rep_probe mlx5r_rep_remove mmap_obj_cleanup modify_qp_mbox_alloc raw_qp_param tx_affinity modify_raw_packet_qp modify_raw_packet_qp_sq notify_soft_wc_handler bytes_mapped pagefault_dmabuf_mr odp_imr user_va pagefault_implicit_mr pagefault_mr odp pagefault_real_mr pagefault_single_data_segment maction is_egress parse_flow_flow_action pkey_change_handler is_fatal_err poll_soft_wc pp_is_supported pp_obj_cleanup process_create_flag process_create_flags process_pma_cmd process_vendor_flag process_vendor_flags query_qp_attr queue_adjust_cache_locked raw_fs_rule_add read_flow_counters reg_create reg_pages_show remove_cache_mr_locked limit_fill resize_available_mrs revoke_mr rsc_event_notifier set_datagram_seg set_mkc_access_pd_addr_fields set_param send_wr set_pi_umr_wr set_port_caps_atomic outer_c outer_v set_proto set_reg_mkey_segment umr set_reg_umr_segment check_not_free set_reg_wr set_roce_addr set_rq_size sig_mr set_sig_data_segment set_srqc set_tos set_ucontext_resp set_user_buf_size set_wq qp_index setup_qp size_read size_write sq_overhead srq_event_notifier npolled is_send sw_comp to_mlx5_st to_rdma_ah_attr uar_mmap new_umem umr_rereg_pas umr_rereg_pd_access validate_rd_atomic var_is_supported